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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration
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A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration

机译：具有可调谐脉冲控制的尖峰延迟收发器，用于低能量无线3-D集成

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摘要

Wireless 3-D integration using inductive coupling links (ICLs) has recently gained attention as a low-cost alternative to through-silicon vias (TSVs) for interconnecting stacked silicon tiers. However, 3-D integration using ICLs is often criticized for its inferior energy efficiency compared with conventional approaches. To address this challenge, in this article, we present a low-energy ICL transceiver that combines a spike-latency encoding scheme (to reduce the number of energy-expensive analog transmit pulses by encoding data in the time domain) and a tunable current driver (to minimize the transmit energy depending on the given integration scenario). The proposed transceiver is modeled mathematically, simulated in 0.35-mu m, 65-nm, and 28-nm CMOS technologies and experimentally validated in a two-tier 3-D stacked silicon test chip. Silicon evaluation of the proposed modulation approach demonstrates an energy of 7.4 pJ/bit, representing a reduction >13% when compared with previously reported schemes (or 7.4% when also considering the additional energy overheads of peripheral clock timing control circuits). The simulated results show even greater energy savings (up to 28%) at more advanced technology nodes. Combined with the adaptive current driver, this results in a 7.7x improvement in energy per bit compared with the state-of-the-art implementations across the same communication distance, marking an important progression toward cost and energy-efficient 3-D integration.
机译：使用电感耦合链路（ICL）的无线3-D集成最近将注意力作为通过用于互连堆叠的硅层的硅通孔（TSV）的低成本替代品。然而，与传统方法相比，使用ICLS的3-D集成通常批评其较差的能效。为了解决这一挑战，在本文中，我们呈现了一个低能量ICL收发器，它结合了尖峰延迟编码方案（通过在时域中的数据编码数据）和可调谐电流驱动器来减少能量昂贵的模拟发送脉冲的数量（根据给定的集成场景，最小化传输能量）。所提出的收发器在数学上进行建模，模拟在0.35-mu m，65-nm和28nm CMOS技术中，并在两层3-D堆叠硅测试芯片中进行实验验证。所提出的调制方法的硅评估显示了7.4 pJ /位的能量，与先前报道的方案相比，表示减少> 13％（或者在考虑到外围时钟时钟定时控制电路的额外能量开销）。模拟结果在更先进的技术节点上表现出更大的节能（高达28％）。结合自适应电流驱动器，这导致每位的能量提高7.7倍，与相同的通信距离相比，标志着成本和节能3-D集成的重要进展。

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