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首页> 外文期刊>IEEE Journal of Solid-State Circuits >The Design of a CMOS Nanoelectrode Array With 4096 Current-Clamp/Voltage-Clamp Amplifiers for Intracellular Recording/Stimulation of Mammalian Neurons
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The Design of a CMOS Nanoelectrode Array With 4096 Current-Clamp/Voltage-Clamp Amplifiers for Intracellular Recording/Stimulation of Mammalian Neurons

机译：具有4096电流钳位/电压 - 钳位放大器的CMOS纳米电极阵列的设计，用于哺乳动物神经元的细胞内记录/刺激

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CMOS microelectrode arrays (MEAs) can record electrophysiological activities of a large number of neurons in parallel but only extracellularly with a low signal-to-noise ratio. Patch-clamp electrodes can perform intracellular recording with a high signal-to-noise ratio but only from a few neurons in parallel. Recently, we have developed and reported a neuroelectronic interface that combines the parallelism of the CMOS MEA and the intracellular sensitivity of the patch clamp. Here, we report the design and characterization of the CMOS integrated circuit (IC), a critical component of the neuroelectronic interface. Fabricated in 0.18-mu m technology, the IC features an array of 4096 platinum black (PtB) nanoelectrodes spaced at a 20-mu m pitch on its surface and contains 4096 active pixel circuits. Each active pixel circuit, consisting of a new switched-capacitor current injector-capable of injecting from +/- 15 pA to +/- 0.7 mu A with a 5-pA resolution-and an operational amplifier, is highly configurable. When configured into the current-clamp mode, the pixel intracellularly records membrane potentials, including subthreshold activities with similar to 23-mu V-rms input-referred noise while injecting a current for simultaneous stimulation. When configured into the voltage-clamp mode, the pixel becomes a switched-capacitor transimpedance amplifier with similar to 1-pA(rms) input-referred noise and intracellularly records ion channel currents while applying a voltage for simultaneous stimulation. Such voltage-/current-clamp intracellular recording/stimulation is a feat only previously possible with the patch-clamp method. At the same time, as an array, the IC overcomes the lack of parallelism of the patch-clamp method, measuring thousands of mammalian neurons in parallel, with full-frame intracellular recording/stimulation at 9.4 kHz.
机译：CMOS微电极阵列（MEAS）可以在并联的大量神经元的电生理活性记录，但仅具有低信噪比的细胞外。贴片钳电极可以以高信噪比进行细胞内记录，但仅从少数神经元并联。最近，我们开发并报告了一种神经电子界面，其结合了CMOS MEA的并行性和贴片夹的细胞内灵敏度。在这里，我们报告了CMOS集成电路（IC）的设计和表征，神经电子界面的关键分量。在0.18-mu M技术中制造，IC具有4096个铂金（PTB）纳米电极的阵列，其表面上的20-mu m间距，并包含4096个有源像素电路。每个有源像素电路，由新的开关电容器电流喷射器组成，能够用5-PA分辨率和运算放大器从+/-15Pa到+/-0.7μma中注入+/-0.7μma。当配置到电流钳位模式中时，像素细胞内记录膜电位，包括具有类似于23-Mu V-RMS输入引用的噪声的亚阈值活性，同时注入用于同时刺激的电流。当配置到电压钳模式时，像素变为具有类似于1-PA（RMS）输入参考噪声的开关电容转换放大器，并且在施加电压以同时刺激的电压时细胞内记录离子通道电流。这种电压/电流夹具细胞内记录/刺激是诸如贴片夹具方法仅可能的壮举。同时，作为阵列，IC克服了斑块夹层方法的缺乏并行性，平行测量成千上万的哺乳动物神经元，具有9.4 kHz的全帧细胞内记录/刺激。

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