A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

Yu Changzhi; Sa Euije; Jin Soowan; Park Himchan; Shin Jongshin; Burm Jinwook

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A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

机译：A 28-NM CMOS中的6.5-12.5-GB / s半速率单环路全数字转印CDR

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This article presents a novel method for frequency tracking based on an extended bang-bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The XBBPD-based structure has a frequency tracking range that completely covers the tuning range of the digitally controlled oscillator (DCO) with a fast locking feature. To minimize the loop delay and thereby improve the jitter tolerance, the CDR design includes an additional proportional path that is realized by directly controlling the phase of the oscillator with the output signal of the phase detector. The design is all-digital, including digital filters that simplify the design. The CDR occupies an active area of 0.031 mm(2), implemented in a 28-nm CMOS process. The receiver operates up to 12.5 Gb/s. The frequency locking time, measured as the time required for every 1-Gb/s change in the input data, is 320 ns. The power consumption is only 21.13 mW, corresponding to an energy efficiency of 2.11 pJ/bit.

机译：本文提出了一种基于引用时钟和数据恢复（CDR）电路中的扩展Bang-Bang相位检测器（XBBPD）的频率跟踪方法。基于XBBPD的结构具有频率跟踪范围，该频率跟踪范围与快速锁定特征完全覆盖了数字控制振荡器（DCO）的调谐范围。为了使循环延迟最小化，从而提高抖动公差，CDR设计包括通过直接控制振荡器的振荡器的相位与相位检测器的输出信号来实现的附加比例路径。该设计是全数字的，包括简化设计的数字滤波器。 CDR占据0.031mm（2）的有源区，在28nm CMOS过程中实施。接收器运行高达12.5 GB / s。频率锁定时间，测量为每1-Gb / s的输入数据所需的时间，是320 ns。功耗仅为21.13 MW，对应于2.11 PJ /位的能量效率。

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来源
《IEEE Journal of Solid-State Circuits》 |2020年第10期|2831-2841|共11页
作者
Yu Changzhi; Sa Euije; Jin Soowan; Park Himchan; Shin Jongshin; Burm Jinwook;
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作者单位

Sogang Univ Dept Elect Engn Seoul 04107 South Korea;

SK Hynix Icheon 17336 South Korea;

LG Elect Seoul 06772 South Korea;

Sogang Univ Dept Elect Engn Seoul 04107 South Korea;

Samsung Elect Co Ltd Foundry Div Hwaseong 18448 South Korea;

Sogang Univ Dept Elect Engn Seoul 04107 South Korea;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
Digital loop filter; digitally controlled oscillator (DCO); extended bang-bang phase detector (XBBPD); half-rate sampling; high-speed integrated circuits; referenceless clock and data recovery (CDR);

机译：数字环路过滤器;数字控制振荡器（DCO）;扩展BANG-BANG相位检测器（XBBPD）;半速率采样;高速集成电路;引用时钟和数据恢复（CDR）;

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专利

1. Referenceless single-loop CDR with a half-rate linear PD and frequency acquisition technique [J] . Kim H. R., Chun J. -H. Electronics Letters . 2020,第5期

机译：引用单环CDR，具有半速率线性PD和频率采集技术
2. All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector [J] . Changzhi Yu, Himchan Park, Qiwei Huang, IEICE Electronics Express . 2020,第6期

机译：全数字半速率由非对称二进制相位检测器具有单向频率扫描方案的All-Digital Alf-rotuel CDR
3. A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS [J] . Wahid Rahman, Danny Yoo, Joshua Liang, Solid-State Circuits, IEEE Journal of . 2017,第12期

机译：在28nm CMOS中具有DFE和CTLE的22.5至32-Gb / s 3.2pJ / b无参考波特率数字CDR
4. 6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS [C] . Kwanseo Park, Minkyo Shim, Han-Gon Ko, IEEE International Solid- State Circuits Conference . 2020

机译：6.5 A 6.4-to-32Gb / s 0.96pJ / b无参考CDR，采用ML启发式40nm CMOS随机相位频率检测技术
5. High speed serial data transmission integrated circuits with half-rate clock and quarter-rate clock in silicon germanium BiCMOS technology. [D] . Yim, Young Uk. 2006

机译：采用硅锗BiCMOS技术的具有半速率时钟和四分之一速率时钟的高速串行数据传输集成电路。
6. Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process [O] . Ruibo Chen, Hongxia Liu, Wenqiang Song, 2020

机译：具有嵌入式PMOSFET的鲁棒和锁定的免疫LVTSCR器件用于28 nm CMOS过程中的ESD保护
7. A Reference-Less Single-Loop Half-Rate Binary CDR [O] . Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, 2015

机译：参考单环半速率二进制CDR
8. Geiger-Mode Avalanche Photodiode Arrays Integrated to All-Digital CMOS Circuits. [R] . Aull, B. F. 2016

机译：Geiger模式雪崩光电二极管阵列集成到全数字CmOs电路。

A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

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