A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

Liu Hui; Xing Xinpeng; Gielen Georges

首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

【24h】

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

机译：一个0-DB STF峰值85-MHz BW 74.4-DB SNDRCTΔςADC，具有28-NM CMOS中的一元近似DAC校准

获取原文

获取原文并翻译 | 示例

掌桥外文数据库（机构版） >>

开具论文收录证明 >>

文献代查 >>

页面导航

摘要
著录项
相似文献
相关主题

摘要

This article presents a continuous-time (CT) Delta Sigma analog-to-digital converter for wireless communication systems with a high tolerance against blockers. The zero-cancellation technique is introduced to eliminate the peaking in the signal transfer function (STF) to achieve better out-of-band-blocker immunity. An on-chip unary-approximating calibration is implemented to calibrate the mismatch of the outer current-steering digital-to-analog converter. A discrete-time (DT) second-order noise-shaping (NS) 2b/cycle asynchronous successive-approximation-register (ASAR) quantizer further reduces the quantization noise and the excess loop delay, achieving a CT-DT hybrid sixth-order NS without suffering from neither the problem of the CT-DT transfer function matching in a CT multistage NS topology nor the stability issue in a singleloop fully CT sixth-order topology. The prototype is fabricated in 28-nm bulk CMOS and is clocked at 1.7 GHz. With a bandwidth of 85 MHz, the analog-to-digital converter achieves 0-dB peaking STF, 74.4-dB signal to noise and SNDR and 87.5-dB spuriousfree dynamic range, while consuming 61.8-mW power, resulting in an excellent Schreier Figure-of-Merit (FoMS) of 165.8 dB.

机译：本文为无线通信系统提供了一种连续时间（CT）Delta Sigma模数转换器，其具有较高的阻塞器的容差。引入零消除技术以消除信号传递函数（STF）中的峰值，以实现更好的带状阻滞剂免疫力。实现了片上的近似校准，以校准外电流转向数模转换器的不匹配。离散时间（DT）二阶噪声整形（NS）2B /周期异步连续近似寄存器（ASAR）量化器进一步降低了量化噪声和过量的循环延迟，实现了CT-DT混合第六阶NS在不遭受CT多级NS拓扑中匹配的CT-DT传递函数匹配的问题，也不是SINGLELOOP中的稳定性问题完全CT第六级拓扑。原型由28-nm散装CMOS制造，并在1.7 GHz时钟。对于85 MHz的带宽，模数转换器达到0-DB峰值STF，74.4-DB信号到噪声和SNDR和87.5-DB的超微直动态范围，同时消耗了61.8兆瓦的功率，导致优秀的施莱尔图-of-merit（foms）为165.8 dB。

著录项

来源
《IEEE Journal of Solid-State Circuits》 |2021年第1期|287-297|共11页
作者
Liu Hui; Xing Xinpeng; Gielen Georges;
展开▼
作者单位

Katholieke Univ Leuven Dept Elect Engn ESAT MICAS Res Grp B-3001 Leuven Belgium;

Tsinghua Univ Grad Sch Shenzhen Shenzhen 518055 Peoples R China;

Katholieke Univ Leuven Dept Elect Engn ESAT MICAS Res Grp B-3001 Leuven Belgium;

展开▼
收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类
关键词
2 b/cycle asynchronous successive-approximation-register (ASAR); continuous-time (CT) Delta Sigma analog-to-digital converter (ADC); flat signal transfer function (STF); noise-shaping (NS) QTZ; on-chip digital-to-analog converter (DAC) calibration; out-of-band blocker (OBB);

机译：2 B /循环异步连续逼近 - 寄存器（ASAR）;连续时间（CT）DERTA SIGMA模数转换器（ADC）;扁平信号传递函数（STF）;噪声整形（NS）QTZ;ON-芯片数模转换器（DAC）校准;带外阻滞剂（OBB）;

相似文献

外文文献
专利

1. An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS [J] . Yun-Shiang Shu, Liang-Ting Kuo, Tien-Yu Lo Solid-State Circuits, IEEE Journal of . 2016,第12期

机译：具有DAC不匹配误差整形的过采样SAR ADC在55 nm CMOS中在1 kHz BW上可实现105 dB SFDR和101 dB SNDR
2. An 85-MHz-BW ASAR-Assisted CT 4-0 MASH $DeltaSigma$ Modulator With Background Half-Range Dithering-Based DAC Calibration in 28-nm CMOS [J] . Liu Hui, Xing Xinpeng, Gielen Georges G. E. IEEE transactions on circuits and systems . I , Regular papers . 2019,第7期

机译：85 MHz BW ASAR辅助CT 4-0 MASH $ Delta Sigma $ 具有基于28nm CMOS的基于背景半范围抖动的DAC校准的调制器
3. A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS [J] . Guanhua Wang, Kexu Sun, Qing Zhang, IEEE transactions on very large scale integration (VLSI) systems . 2019,第9期

机译：具有背景校准的精细和粗糙比较器的43.6dB SNDR 1-GS / s 3.2mW SAR ADC，采用28nm CMOS
4. An 85MHz-BW 68.5dB-SNDR ASAR-assisted CT 4-0 MASH ΔΣ modulator with half-range dithering-based DAC calibration in 28nm CMOS [C] . Hui Liu, Xinpeng Xing, Georges Gielen IEEE Custom Integrated Circuits Conference . 2018

机译：一个85MHz-BW 68.5dB-SNDR ASAR辅助CT 4-0 MASHΔΣ调制器，在28nm CMOS中具有基于半程抖动的DAC校准
5. Power reduction techniques for CMOS current mode pipelined ADCs. [D] . Chan, Chi Hong. 2007

机译：CMOS电流模式流水线ADC的功耗降低技术。
6. Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process [O] . Ruibo Chen, Hongxia Liu, Wenqiang Song, 2020

机译：具有嵌入式PMOSFET的鲁棒和锁定的免疫LVTSCR器件用于28 nm CMOS过程中的ESD保护
7. A 0.2-to-2MHz BW, 50-to-86dB SNDR, 16-to-22mW Flexible 4th-Order ΣΔ modulator with DC-to-44MHz tunable center frequency in 1.2-V 90-nm CMOS [O] . Asghar, S., Río, Rocío del, Rosa, José M. de la 2013

机译：一个0.2至2MHz带宽，50至86dB SNDR，16至22mW灵活的四阶ΣΔ调制器，在1.2V 90nm CMOS中具有DC至44MHz可调中心频率

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

摘要

著录项

相似文献

相关主题

期刊订阅