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All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits

机译：用于测量数字电路中空间变化的全数字电路

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Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates spatial variation in digital circuit performance: we describe a test-chip in 90 nm CMOS containing all-digital measurement circuits capable of extracting accurate variation data. Specifically, we use replicated 64-bit Kogge-Stone adders, ring oscillators (ROs) of varying gate type and stage length and an all-digital, sub-picosecond resolution delay measurement circuit to provide this data. Measurement data from the test-chips indicate that 1) relative variation is significantly larger in low-voltage domains, 2) within-die variation is spatially uncorrelated, and 3) die-to-die (or global) variation is strongly correlated, but degrades toward uncorrelated as the power-supply voltage is lowered. Lastly, extended analysis of the data reveals that systematic effects such as layout pattern dependencies or circuit structure can be misinterpreted as random but spatially-correlated variation. This suggests that circuit designers will reap more benefit from design tools capable of modeling systematic, position-dependent variation rather than spatially correlated, distance-dependent variation.
机译：由于缩放导致CMOS工艺变化的增加，导致在开发电路方法以减轻变化时更加依赖精确的变化模型。本文研究了数字电路性能的空间变化：我们描述了一种包含全数字测量电路的90 nm CMOS测试芯片，该电路能够提取准确的变化数据。具体来说，我们使用复制的64位Kogge-Stone加法器，不同栅极类型和级长度的环形振荡器（RO）以及全数字，亚皮秒分辨率延迟测量电路来提供此数据。来自测试芯片的测量数据表明：1）低压域中的相对变化明显更大； 2）芯片内的变化在空间上不相关； 3）芯片到芯片（或全局）的变化密切相关，但是随着电源电压的降低，降级将变得不相关。最后，对数据的扩展分析表明，诸如布局模式依赖性或电路结构之类的系统效应可能被误解为随机但与空间相关的变化。这表明电路设计人员将从能够建模系统的，与位置相关的变化而不是与空间相关的，与距离相关的变化建模的设计工具中获得更多收益。

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