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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter
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A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter

机译：具有集成SRAM和开关电容DC-DC转换器的65 nm Sub- $ V_ {t} $微控制器

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摘要

Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V DD of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power.
机译：积极地将电源电压缩放到低于器件阈值电压，可在逻辑和SRAM电路中显着降低能耗并降低功耗。因此，对于性能要求宽松的能源受限系统而言，这是一种引人注目的策略。但是，工艺变化的影响在低电压下变得更加突出，尤其是在深度扩展技术中。本文介绍了一个65 nm的片上系统，该芯片演示了缓解变化的技术，可实现低至300 mV的亚阈值工作。 16位微控制器内核设计有自定义的亚阈值单元库和时序方法，可解决逻辑门中的输出电压故障和传播延迟。 128 kb SRAM使用8 T位单元来确保读取稳定性，并使用外围辅助电路来允许对亚Vt进行读写。逻辑和SRAM功能在300 mV至600 mV的范围内，在500 mV的最佳V DD时消耗27.2 pJ /周期，在300 mV的情况下待机功耗为1μW。为了在这些低功率水平下提供可变电压，片上集成了开关电容器DC-DC转换器，可实现75％以上的效率，同时提供10μW至250μW的负载功率。

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