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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology
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A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

机译:3.8 GHz 153 Mb SRAM设计具有动态稳定性增强和减少泄漏的45 nm High-k Metal Gate CMOS技术

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摘要

A high-performance low-power 153 Mb SRAM is developed in 45 nm high-k Metal Gate technology. Dynamic SRAM PMOS forward-body-bias (FBB) and Active-Controlled SRAM VCC in Sleep are integrated in the design to lower Active-VCCmin and Standby Leakage, respectively. FBB improves the Active-VCCmin by up to 75 mV, and Active-Controlled SRAM VCC distribution tightened by 100 mV, both of which result in further power reduction. A 0.346 mum2 6T-SRAM bit-cell is used which is optimized for VCCmin, performance, leakage and area. The design operates at high-speed over a wide voltage range, and has a maximum frequency of 3.8 GHz at 1.1 V. The 16 KB Subarray was also used as the building block in on-die 6 MB Cache for Intel Core 2 Duo CPU in 45 nm technology.
机译:高性能低功耗153 Mb SRAM采用45 nm高k金属栅极技术开发。设计中集成了动态SRAM PMOS前向体偏置(FBB)和处于睡眠状态的有源控制SRAM VCC,分别降低了Active-VCCmin和待机泄漏。 FBB将Active-VCCmin提高了高达75 mV,Active-Controlled SRAM VCC分配提高了100 mV,这两者都进一步降低了功耗。使用0.346 mum2 6T-SRAM位单元,针对VCCmin,性能,泄漏和面积进行了优化。该设计可在较宽的电压范围内高速运行,并且在1.1 V时的最大频率为3.8GHz。16KB子阵列还用作英特尔®酷睿TM 2 Duo CPU的片上6 MB高速缓存的构件。 45 nm技术。

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