A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU

Ito M.; Nitta K.; Ohno K.; Saigusa M.; Nishida M.; Yoshioka S.; Irita T.; Koike T.; Kamei T.; Komuro T.; Hattori T.; Arai Y.; Kodama Y.

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A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU

机译：具有部分时钟激活和IP-MMU的65 nm单芯片应用和双模式基带处理器

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Supporting both WCDMA with HSDPA and GSM/GPRS/EDGE, the $hbox{9.3}times hbox{9.3} {hbox{mm}}^{2}$ SoC fabricated in triple-Vth 65nm CMOS, has three CPU cores and 20 separate power domains. Unused power domains can be powered down to reduce the leakage power. Partial clock activation scheme especially focused on music playback scene dynamically stops a PLL and clock trees when not necessary and reduces power consumption from 33.6 mW to 19.6 mW. IP-MMU translates virtual address to physical address for 18 hardware-IPs and virtual address space can be allocated when necessary and can be freed after its operation, reducing external memory by 43 MB. Video performance of D1 (720 $times$ 520) size with 30 frames per second for MPEG/AVC decoding and encoding can be achieved under mixed virtual and physical address usage.

机译：支持三速Vth 65nm CMOS的$ hbox {9.3}乘以hbox {9.3} {hbox {mm}} ^ {2} $ SoC既支持HSDPA的WCDMA，又支持GSM / GPRS / EDGE，具有三个CPU内核和20个独立内核电源域。可以关闭未使用的电源域以降低泄漏功率。专门针对音乐播放场景的部分时钟激活方案在不需要时会动态停止PLL和时钟树，并将功耗从33.6 mW降低到19.6 mW。 IP-MMU将虚拟地址转换为18个硬件IP的物理地址，并且可以在必要时分配虚拟地址空间，并且在其运行后可以将其释放，从而将外部内存减少了43 MB。在混合使用虚拟地址和物理地址的情况下，可以实现D1（720 x 520）每秒30帧的MPEG / AVC解码和编码的视频性能。

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来源
《IEEE Journal of Solid-State Circuits》 |2009年第1期|p.83-89|共7页
作者
Ito M.; Nitta K.; Ohno K.; Saigusa M.; Nishida M.; Yoshioka S.; Irita T.; Koike T.; Kamei T.; Komuro T.; Hattori T.; Arai Y.; Kodama Y.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
Application processor; baseband processor; cellular phone; clock activation; memory space; power domains;

机译：应用处理器;基带处理器;手机;时钟激活;内存空间;电源域;

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A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU

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