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首页> 外文期刊>IEEE Journal of Solid-State Circuits >An 8.29 mm$^{2}$ 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 $mu$m CMOS Process
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An 8.29 mm$^{2}$ 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 $mu$m CMOS Process

机译:用于移动WiMAX系统的8.29 mm $ ^ {2} $ 52 mW多模式LDPC解码器设计,采用0.13 $ mu $ m CMOS工艺

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摘要

This paper presents a multi-mode decoder design for Quasi-Cyclic LDPC codes for Mobile WiMAX system. This chip can be operated in 19 kinds of modes specified in Mobile WiMAX system, including block sizes of 576, $ldots$, 2304. There are four proposed design techniques: reordering of the base matrix, overlapped operations of main computational units, early termination strategy and multi-mode design strategy. Based on overlapped decoding mechanism, the decoding latency can be reduced to 68.75% of non-overlapped method, and the hardware utilization ratio can be enhanced from 50% to 75%. Besides, the proposed early termination strategy can dynamically adjust the number of iterations when dealing with communication channels of different SNR values. The proposed multi-mode LDPC decoder design is implemented and fabricated in TSMC 0.13 $mu$ m 1.2 V 1P8M CMOS technology. The maximum operating frequency is measured 83.3 MHz and the corresponding power dissipation is 52 mW. The core size is 4.45 ${hbox {mm}}^{2}$ and the die area only occupies 8.29 ${hbox {mm}}^{2}$.
机译:本文提出了一种用于移动WiMAX系统的准循环LDPC码的多模式解码器设计。该芯片可以在Mobile WiMAX系统中指定的19种模式下运行,包括块大小为576,$ ldots $,2304。建议的设计技术有四种:基本矩阵的重新排序,主要计算单元的重叠操作,提前终止。策略和多模式设计策略。基于重叠解码机制,可以将解码延迟降低到非重叠方法的68.75%,并将硬件利用率从50%提高到75%。此外,提出的提早终止策略可以在处理不同SNR值的通信信道时动态调整迭代次数。所提出的多模式LDPC解码器设计是在TSMC 0.13μm1.2 V 1P8M CMOS技术中实现和制造的。测得的最大工作频率为83.3 MHz,相应的功耗为52 mW。核心尺寸为4.45 $ {hbox {mm}} ^ {2} $,而芯片面积仅占8.29 $ {hbox {mm}} ^ {2} $。

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