A 1.2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-$mu{hbox{m}}$ CMOS

Jussila J.; Sivonen P.

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A 1.2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-$mu{hbox{m}}$ CMOS

机译：采用0.13- $ mu {hbox {m}} $ CMOS的1.2V高度线性平衡噪声消除LNA

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In this paper, a current-to-voltage combiner is proposed to realize a highly linear, balanced noise-cancelling low-noise amplifier (LNA) capable of low-voltage operation. The current-to-voltage combiner, implemented in the load of the amplifier, converts the output currents of the parallel common-gate (CG) and common-source (CS) stages of the LNA to voltages, equalizes the amplitudes of the voltages, and combines the voltages to a single output voltage. Since only a CS stage and passive components are employed to cancel the noise and distortion due to the CG input impedance matching circuit, high linearity is achieved in spite of the low supply voltage of 1.2 V. The LNA achieves a noise figure (NF) of 3.0 dB at 2.1 GHz with an input-referred third-order intercept point (IIP3) of $+$10.5 dBm while consuming 10.5 mA from a 1.2-V supply. The amplifier is fabricated in 0.13-$mu{hbox{m}}$ CMOS process.

机译：本文提出了一种电流电压组合器，以实现一种能够在低压下工作的高度线性，平衡的消除噪声的低噪声放大器（LNA）。在放大器的负载中实现的电流电压合成器将LNA的并行共栅（CG）和共源（CS）级的输出电流转换为电压，以均衡电压幅度，并将这些电压组合成一个输出电压。由于仅使用CS级和无源元件来消除CG输入阻抗匹配电路带来的噪声和失真，因此尽管电源电压低至1.2 V，仍可实现高线性度。LNA的噪声系数（NF）为在2.1 GHz时为3.0 dB，输入参考的三阶交调点（IIP3）为$ + $ 10.5 dBm，而1.2V电源的功耗为10.5 mA。该放大器采用0.13-μmu{hbox {m}} $ CMOS工艺制造。

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来源
《IEEE Journal of Solid-State Circuits》 |2008年第3期|p.579-587|共9页
作者
Jussila J.; Sivonen P.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CMOS analog integrated circuits; low-noise amplifiers (LNA); noise cancelling; radio frequency integrated circuits;

机译：CMOS模拟集成电路;低噪声放大器（LNA）;消噪;射频集成电路;

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1. Symmetric Offset Stack Balun in Standard 0.13-$mu{hbox {m}}$ CMOS Technology for Three Broadband and Low-Loss Balanced Passive Mixer Designs [J] . Chiou H.-K., Lin J.-Y. Microwave Theory and Techniques, IEEE Transactions on . 2011,第6期

机译：标准0.13- $ mu {hbox {m}} $ CMOS技术中的对称偏移堆栈巴伦，用于三种宽带和低损耗平衡无源混频器设计
2. Temperature Effect on $Ku$-Band Current-Reused Common-Gate LNA in 0.13-$mu{hbox{m}}$ CMOS Technology [J] . Chen W.-L., Chang S.-F., Chen K.-M., Microwave Theory and Techniques, IEEE Transactions on . 2009,第9期

机译：温度对0.13- $ mu {hbox {m}} $ CMOS技术中$ Ku $频段电流复用共栅LNA的温度影响
3. A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13- $mu$m CMOS Technology [J] . Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu IEEE Journal of Solid-State Circuits . 2007,第6期

机译：采用0.13-μmCMOS技术的1.2V 37-38.5GHz八相时钟发生器
4. A 1.2-V 10-Gb/s Highly C_(PD) Isolated and Bandwidth Enhanced Optical Receiver in 0.13-(mu)m CMOS Technology [C] . W. S. Oh, K. Park, K. W. Min, International Conference on Advanced Communication Technology . 2009

机译：1.2-V 10 GB / s高度C_（PD）隔离和带宽增强光接收器，在0.13-（MU）M CMOS技术中
5. Designs of broadband highly linear CMOS LNAs for multiradio multimode applications. [D] . Chen, Wei-Hung. 2009

机译：用于多无线电多模应用的宽带高度线性CMOS LNA设计。
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7. Development of Accurate BSIM4 Noise Parameters for CMOS 0.13-µm Transistors in Below 3-GHz LNA Application [O] . Asmaa Nur Aqilah Zainal Badri, Norlaili Mohd Noh, Shukri Bin Korakkottil Kunhi Mohd, 2018

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A 1.2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-$mu{hbox{m}}$ CMOS

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