...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>IEEE Journal of Solid-State Circuits >40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS
【24h】

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

机译：用于90 nm CMOS的宽带数据接收器的40 Gb / s跨阻AGC放大器和CDR电路

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 ${rm k}Omega$ and a differential output swing of $520{rm mV}_{rm pp}$ with ${hbox{BER}}≪10^{-9}$ for input spanning from $430mu{hbox {A}}_{rm pp}$ to $4{hbox {mA}}_{rm pp}$ . The measured integrated input-referred noise is $3.3mu{hbox {A}}_{rm rms}$. The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s $2^{31}-1$ PRBS input, the recovered clock jitter is $0.7{hbox {ps}}_{rm rms}$ and $5.6{hbox {ps}}_{rm pp}$ . The retimed data exhibits $13.3{hbox {ps}}_{rm pp}$ jitter with ${hbox{BER}}≪10^{-9}$. Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply.
机译：高速前端放大器和CDR电路在宽带数据接收器中起着至关重要的作用，因为前者需要以高数据速率执行放大，而后者则必须利用提取的低抖动时钟对数据进行重新计时。本文介绍了40 Gb / s跨阻AGC放大器和CDR电路的设计和实验结果。跨阻放大器在公共栅极配置中集成了反向三谐振网络（RTRN）和负反馈。推导了一个数学模型以简化RTRN的设计和分析，结果表明，与使用并联串联峰值技术相比，带宽扩展了更大的因数，特别是在寄生电容由下一级决定的情况下。该放大器工作在40 Gb / s的速度下，总增益为2 $ {rm k} Omega $，差分输出摆幅为$ 520 {rm mV} _ {rm pp} $，其中$ {hbox {BER}} ≪10 ^ {-9} $用于输入，范围从$ 430mu {hbox {A}} _ {rm pp} $到$ 4 {hbox {mA}} _ {rm pp} $。测得的积分输入噪声为$ 3.3mu {hbox {A}} _ {rm rms} $。半速率CDR电路采用方向确定的旋转波正交VCO来解决传统旋转波振荡器中的双向旋转问题。这保证了相序，而对相位噪声的影响可忽略不计。使用40 Gb / s的$ 2 ^ {31} -1 $ PRBS输入，恢复的时钟抖动为$ 0.7 {hbox {ps}} _ {rm rms} $和$ 5.6 {hbox {ps}} _ {rm pp} $。重新计时的数据表现出$ 13.3 {hbox {ps}} _ {rm pp} $的抖动与$ {hbox {BER}} ≪10 ^ {-9} $。采用90 nm数字CMOS技术制造，整个放大器的功耗为75 mW，而CDR电路的功耗为48 mW（不包括输出缓冲器），均来自1.2 V电源。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号