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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue
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A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue

机译：90 nm CMOS中的9b，1.25 ps分辨率粗精细时间数字转换器，可放大时间残差

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摘要

This paper presents the design of a coarse–fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, similar to a coarse–fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time residue with a higher gain ($> $16) and larger range ($> $80 ps) than existing solutions do. However, adapting the conventional coarse–fine architecture from ADCs is not an appropriate solution for TDCs: input time cannot be stored, and the gain of a time amplifier (TA) cannot be controlled precisely. This paper proposes a new coarse–fine TDC architecture by using an array of time amplifiers and two identical fine TDCs that compensate for the variation of the TA gain during the conversion process. The measured DNL and INL are ${pm} $0.8 LSB and ${pm} $3 LSB, respectively, with a value of 1.25 ps per 1 LSB, while the standard deviation of output code for constant inputs remains below 1 LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.
机译：本文介绍了一种粗细时间数字转换器（TDC）的设计，它可以放大时间残差以提高时间分辨率，类似于粗细模拟数字转换器（ADC）。已经开发了一种新的数字电路，以比现有技术具有更高的增益（$> $ 16）和更大的范围（$> $ 80 ps）来放大时间残差。解决方案。然而，采用传统的ADC的粗细结构对TDC来说不是合适的解决方案：无法存储输入时间，并且无法精确控制时间放大器（TA）的增益。本文通过使用时间放大器阵列和两个相同的精细TDC来提出新的粗精细TDC体系结构，以补偿转换过程中TA增益的变化。测得的DNL和INL分别为$ {pm} $ 0.8 LSB和$ {pm} $ 3 LSB，每1 LSB值为1.25 ps，而恒定输入的输出代码的标准偏差在TDC范围内保持低于1 LSB。尽管非线性度大于1 LSB，但使用INL查找表或在粗略TDC延迟链中使用更好的匹配延迟将进一步改善线性度。

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