A Low Power V-Band CMOS Frequency Divider With Wide Locking Range and Accurate Quadrature Output Phases

Gu Q.; Xu Z.; Huang D.; LaRocca T.; Wang N.-Y.; Hant W.; Chang M.-C. F.

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A Low Power V-Band CMOS Frequency Divider With Wide Locking Range and Accurate Quadrature Output Phases

机译：具有宽锁定范围和精确正交输出相位的低功耗V波段CMOS分频器

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摘要

A new injection-locked frequency divider (ILFD) circuit topology, by combining the strengths of LC type ILFD (LC_ILFD) and ring oscillator type ILFD (RO_ILFD), is proposed to achieve high speed, low power, wide locking range and accurate quadrature output phases. The frequency-division criterion is analyzed and agrees well with simulation results. The phase-locking mechanism is also investigated with emphasis on its resilience to device and circuit mismatches. A prototype is implemented in TSMC 90 nm CMOS to validate the effective locking range of 7.4 GHz (53.4 to 60.8 GHz) with 0 dBm input signal and 5 mW DC power dissipation. The circuit attains the highest figure-of-merit (dividing frequency/power) to date for V-band frequency dividers implemented in deep-scaled CMOS technologies.

机译：通过结合LC型ILFD（LC_ILFD）和环形振荡器型ILFD（RO_ILFD）的优势，提出了一种新的注入锁定分频器（ILFD）电路拓扑，以实现高速，低功耗，宽锁定范围和准确的正交输出阶段。分析了分频准则，并与仿真结果吻合良好。还研究了锁相机制，强调其对器件和电路失配的适应性。在TSMC 90 nm CMOS中实现了原型，以在输入信号为0 dBm和直流功耗为5 mW的情况下验证7.4 GHz（53.4至60.8 GHz）的有效锁定范围。对于以深层CMOS技术实现的V波段分频器，该电路具有迄今为止最高的品质因数（分频/功率）。

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来源
《IEEE Journal of Solid-State Circuits》 |2008年第4期|p.991-998|共8页
作者
Gu Q.; Xu Z.; Huang D.; LaRocca T.; Wang N.-Y.; Hant W.; Chang M.-C. F.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
Accurate quadrature phase; RF CMOS; injection-locked frequency divider; low power consumption; phase noise; wide locking range;

机译：精确的正交相位;RF CMOS;注入锁定分频器;低功耗;相位噪声;宽锁定范围;

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1. A V-Band CMOS Low-DC-Power Wide-Locking-Range Divide-by-6 Injection-Locked Frequency Divider Using Transformer Coupling [J] . Chang Hong-Yeh, Chen Wei-Cheng, Yeh Han-Non, IEEE microwave and wireless components letters . 2020,第6期

机译：V波段CMOS低直流电源宽锁定范围除以6锁定分频器，使用变压器耦合
2. A V-Band Divide-by-Four Frequency Divider With Wide Locking Range and Quadrature Outputs [J] . Yu C.-A., Luo T.-N., Chen Y.-J. E. Microwave and Wireless Components Letters, IEEE . 2012,第2期

机译：具有宽锁定范围和正交输出的V频段四分频分频器
3. LOW POWER WIDE-LOCKING RANGE CMOS QUADRATURE INJECTIONLOCKED FREQUENCY DIVIDER [J] . Sheng-Lyang Jang, Chia-Wei Chang, Sheng-Ming Yang Microwave and optical technology letters . 2009,第10期

机译：低功耗广锁范围CMOS正交注入锁定频率分频器
4. A Wide Locking Range and Low Power V-band Frequency Divider in 90nm CMOS [C] . Qun Gu, Zhiwei Xu, Chang, VLSI Circuits, 2007 IEEE Symposium on . 2007

机译：90nm CMOS的宽锁定范围和低功耗V波段分频器
5. A Low Power CMOS Phase-Locked Loop Frequency Synthesizer for High Frequency Applications with Integer-N Frequency Divider [D] . Tan, Nurettin. 2016

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6. Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications [O] . Bilal I. Abdulrazzaq, Omar J. Ibrahim, Shoji Kawahito, 2016

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7. Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS [O] . Behzad Razavi, Kwing F. Lee, Ran H. Yan 1995

机译：深亚微米CMOS中的高速，低功率分频器和锁相环的设计

A Low Power V-Band CMOS Frequency Divider With Wide Locking Range and Accurate Quadrature Output Phases

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