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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A Variable-Phase Ring Oscillator and PLL Architecture for Integrated Phased Array Transceivers
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A Variable-Phase Ring Oscillator and PLL Architecture for Integrated Phased Array Transceivers

机译：集成相控阵收发器的可变相位环形振荡器和PLL架构

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摘要

A variable-phase ring oscillator (VPRO) and phase-locked loop (PLL) architecture is introduced for integrated phased arrays. The architecture eliminates key building blocks such as mixers, phase shifters and power splitters/combiners, allowing for compact and low-power implementations. This paper presents the principles of operation of the architecture in transmit and receive modes, along with a detailed theoretical treatment of critical performance metrics such as linearity and sensitivity. In addition, measured results from a prototype, 24 GHz , 4-channel, phased-array transceiver, implemented in a 0.13$ mu{hbox{m}}$ CMOS process, are presented.
机译：针对集成相控阵引入了可变相位环形振荡器（VPRO）和锁相环（PLL）体系结构。该架构消除了关键的构建模块，例如混频器，移相器和功率分配器/组合器，从而实现了紧凑和低功耗的实现。本文介绍了在发送和接收模式下架构的工作原理，以及对关键性能指标（如线性和灵敏度）的详细理论处理。此外，还介绍了采用0.13μmCMOS工艺实现的原型24 GHz，4通道，相控阵收发器的测量结果。

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