A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC

Brooks L.; Lee H.-S.

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A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC

机译：基于零交叉的8位200 MS / s流水线ADC

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摘要

Zero-crossing-based circuits (ZCBC) are introduced as a generalization of comparator-based switched-capacitor circuits (CBSC). To demonstrate this concept, an 8-bit, 200 MS/s, pipelined ADC is implemented in a 0.18 $mu{hbox{m}}$ CMOS technology. A dynamic zero-crossing detector and current source replace the functionality of an opamp to realize a precision charge transfer. Furthermore, current source splitting improves linearity at high speeds and bit decision flip-flops replace traditional bit decision comparators for increased speed. The complete ADC draws no static current and consumes 8.5 mW of power. The corresponding FOM is 0.38 pJ/step at 100 MS/s and 0.51 pJ/step at 200 MS/s.

机译：引入基于零交叉的电路（ZCBC）作为基于比较器的开关电容电路（CBSC）的概括。为了证明这一概念，采用0.18μmCMOS技术实现了8位，200 MS / s的流水线ADC。动态过零检测器和电流源取代了运算放大器的功能，可实现精确的电荷转移。此外，电流源分裂提高了高速时的线性度，并且位判决触发器取代了传统的位判决比较器以提高速度。完整的ADC不消耗静态电流，消耗8.5 mW的功率。相应的FOM在100 MS / s下为0.38 pJ /步，在200 MS / s下为0.51 pJ /步。

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来源
《IEEE Journal of Solid-State Circuits》 |2007年第12期|p.2677-2687|共11页
作者
Brooks L.; Lee H.-S.;
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作者单位

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
Analog-to-digital conversion (A/D); analog-to-digital converter (ADC); comparator-based switched-capacitor circuits (CBSC); scaled CMOS; zero-crossing-based circuits (ZCBC);

机译：模数转换（A / D）;模数转换器（ADC）;基于比较器的开关电容器电路（CBSC）;缩放的CMOS;基于零交叉的电路（ZCBC）;

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1. A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration [J] . Shin S.-K., Rudell J.C., Daly D.C., IEEE Journal of Solid-State Circuits . 2014,第6期

机译：具有早期子ADC决策和输出残留背景校准的12位200 MS / s基于零交叉的流水线ADC
2. A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13- src="/images/tex/21769.gif" alt="mu "> m CMOS Technology [J] . Chu Myonglae, Kim Byoungho, Lee Byung-Geun Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2015,第11期

机译：0.13- src =“ / images / tex / 21769.gif” alt =“ mu”> 的10位200-MS / s基于零交叉的流水线ADC m CMOS技术
3. Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation [J] . Lee H.-Y. Circuits, Devices & Systems, IET . 2011,第5期

机译：基于零交叉的8位100 MS / s流水线模数转换器，具有失调补偿
4. A Zero-Crossing-Based 8b 200MS/s Pipelined ADC [C] . Brooks, L., Hae-Seung Lee . 2007

机译：基于零交叉的8b 200MS / s流水线ADC
5. A 200MS/s 12-bit subranging SAR ADC [D] . Elies, Brian. 2015

机译：一个200ms / s 12位分级SAR ADC
6. pGlyco: a pipeline for the identification of intact N-glycopeptides by using HCD- and CID-MS/MS and MS3 [O] . Wen-Feng Zeng, Ming-Qi Liu, Yang Zhang, -1

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7. A 1-V 690 #x03BC;W 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13#x03BC;m CMOS [O] . Monireh Eslami, Mohammad Taherzadeh-Sani, Frederic Nabki 2015

机译：具有0.13μmCMOS的闪光灯和SAR ADC的1-V690μW8位200 MS / S闪存SAR ADC

A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC

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