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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC
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A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC

机译:具有回开DAC的0.5V 74dB SNDR 25kHz连续时间Δ-Σ调制器

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摘要

A 0.5-V third-order one-bit fully-differential continuous-time DeltaSigma modulator is presented. The presented modulator architecture uses true low-voltage design techniques, and does not require internal voltage boosting or low-threshold devices. A return-to-open architecture that enables the ultra-low-voltage realization of return-to-zero signaling for the feedback DAC is proposed. The ultra-low-voltage operation is further enabled by a body-input gate-clocked comparator, and body-input operational transconductance amplifiers for the active-RC loop filter. Fabricated on a 0.18-mum CMOS process, the modulator achieves a peak SNDR of 74 dB in a 25 kHz bandwidth, and occupies an area of 0.6 mm2; the modulator core consumes 300 muW
机译:提出了一个0.5V三阶一位全差分连续时间DeltaSigma调制器。提出的调制器架构使用了真正的低压设计技术,并且不需要内部升压或低阈值器件。提出了一种开放式架构,该架构可实现超低电压实现反馈DAC的归零信令。主体输入栅极时钟比较器和有源RC环路滤波器的主体输入运算跨导放大器进一步实现了超低压操作。该调制器采用0.18微米CMOS工艺制造,在25 kHz带宽内达到74 dB的峰值SNDR,占用面积为0.6 mm2。调制器内核消耗300μW

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