A 256-Kb Dual-VCC  SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor

Khellah M.; Somasekhar D.; Ye Y.; Kim N. S.; Howard J.; Ruhl G.; Sunna M.; Tschanz J.; Borkar N.; Hamzaoglu F.; Pandya G.; Farhang A.; Zhang K.; De V.

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A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor

机译：采用有源钳位睡眠晶体管的65nm CMOS工艺中的256Kb双VCC SRAM构造块

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This paper addresses the stability problem of SRAM cells used in dense last level caches (LLCs). In order for the LLC not to limit the minimum voltage at which a processor core can run, a dual-VCC 256-Kb SRAM building block is proposed. A fixed high-voltage supply powers the cache which allows the use of the smallest SRAM cell for maximum density, while a separate variable supply is used by the core for ultra-low-voltage operation using dynamic voltage and frequency (DVF). Implemented in a 65-nm bulk CMOS process, the block features low overhead embedded level shifters and an actively clamped sleep transistor for maximum cache leakage power reduction during standby. Measured results show that the proposed block runs at 4.2GHz while consuming 30 mW at 85degC and 1.2V supply. Furthermore, measurements across a wide range of process, voltage, temperature, and aging conditions indicate virtual ground clamping accuracy within a few millivolts of required cache standby VMIN. Extrapolating the 256-Kb block measurement results in a large 64-Mb LLC used in a dual-V CC processor gives 35% reduction in total processor power as compared with a single-VCC processor design running at a high supply voltage

机译：本文解决了用于密集末级高速缓存（LLC）的SRAM单元的稳定性问题。为了使LLC不会限制处理器内核可以运行的最低电压，提出了双VCC 256-Kb SRAM构造块。固定的高压电源为高速缓存供电，从而允许使用最小的SRAM单元以实现最大的密度，而内核使用单独的可变电源通过动态电压和频率（DVF）进行超低压操作。该模块采用65nm批量CMOS工艺实现，具有低开销嵌入式电平转换器和有源钳位睡眠晶体管，可最大程度地降低待机期间的缓存泄漏功率。测量结果表明，该模块在4.2GHz下运行，同时在85℃和1.2V电源下消耗30mW。此外，在广泛的过程，电压，温度和老化条件下进行的测量表明，虚拟接地钳位精度在所需缓存备用VMIN的几毫伏范围内。与在高电源电压下运行的单VCC处理器设计相比，在双V CC处理器中使用的大型64 Mb LLC推断256 Kb块测量结果可将处理器总功耗降低35％

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来源
《IEEE Journal of Solid-State Circuits》 |2007年第1期|p.233-242|共10页
作者
Khellah M.; Somasekhar D.; Ye Y.; Kim N. S.; Howard J.; Ruhl G.; Sunna M.; Tschanz J.; Borkar N.; Hamzaoglu F.; Pandya G.; Farhang A.; Zhang K.; De V.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CMOS integrated circuits; SRAM chips; cache storage; embedded systems; microprocessor chips; transistors; 1.2 V; 256 kBytes; 30 mW; 4.2 GHz; 64 MBytes; 65 nm; 85 C; CMOS process; SRAM building block; SRAM cells stability; cache leakage power reduction; dual-Vcc processor;

机译：CMOS集成电路;SRAM芯片;高速缓存存储;嵌入式系统;微处理器芯片;晶体管;1.2 V;256 kBytes;30 mW;4.2 GHz;64 MBytes;65 nm;85 C;CMOS工艺;SRAM构造块;SRAM单元稳定性;缓存泄漏功率降低;双Vcc处理器;

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专利

1. A 256-Kb Dual-${V}_{rm CC}$ SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor [J] . Khellah M., Somasekhar D., Ye Y., IEEE Journal of Solid-State Circuits . 2007,第期

机译：采用有源钳位睡眠晶体管的65nm CMOS工艺中的256-Kb Dual-$ {V} _ {rm CC} $ SRAM构造模块
2. SRAM Design on 65-nm CMOS Technology With Dynamic Sleep Transistor for Leakage Reduction [J] . Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, IEEE Journal of Solid-State Circuits . 2005,第4期

机译：采用动态睡眠晶体管的65nm CMOS技术的SRAM设计，可减少泄漏
3. A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors [J] . Gabriel Torrens, Bartomeu Alorda, Cristian Carmona, Emerging Topics in Computing, IEEE Transactions on . 2019,第3期

机译：具有最小尺寸晶体管的65nm可靠6T CMOS SRAM单元
4. The multiport CMOS memory cell based on the DICE trigger with two spaced transistor groups for hardened 65-nm CMOS SRAM [C] . Yuri V. Katunin, Vladimir Ya. Stenin International Siberian Conference on Control and Communications . 2016

机译：基于骰子触发器的多端口CMOS存储器单元，用于硬化为65-NM CMOS SRAM的两个间隔晶体管组
5. W-band passive and active circuits in 65-nm bulk CMOS for passive imaging applications. [D] . Tomkins, Alexander. 2010

机译：65纳米体CMOS中的W波段无源和有源电路，用于无源成像应用。
6. A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process [O] . Meng-Yin Hsu, Chu-Feng Liao, Yi-Hong Shih, 2017

机译：采用纯CMOS逻辑工艺的具有自抑制电阻切换负载的RRAM集成4T SRAM
7. Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process [O] . Guangyi Lu, Yuan Wang, Lizhong Zhang, 2016

机译：65-NM CMOS工艺中的新型静电触发电源轨ESD钳电路的设计

A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor

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