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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A Low-Dropout Regulator for SoC With Q-Reduction
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A Low-Dropout Regulator for SoC With Q-Reduction

机译:具有降Q功能的SoC低压降稳压器

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A low-dropout regulator for SoC, with an advanced Q-reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 muA, is introduced in this paper. The idea has been implemented in a standard 0.35-mum CMOS technology (VTHN ap 0.55 V and |VTHP| ap 0.75 V). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without Q-reduction circuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current
机译:本文介绍了一种用于SoC的低压降稳压器,该稳压器具有先进的Q减小电路,可将片上电容和最小输出电流要求降至100μA(最小)。该想法已在标准的0.35微米CMOS技术(VTHN约为0.55 V和| VTHP |约为0.75 V)中实现。所需的片上电容降至6 pF,而无Q减小电路的情况则为25 pF。从实验结果来看,拟议的稳压器电路实现可将电压调节至低至1.2V的电源电压,在最大输出电流为100mA时的压降为200mV。

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