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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A Three-Data Differential Signaling Over Four Conductors With Pre-Emphasis and Equalization: A CMOS Current Mode Implementation
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A Three-Data Differential Signaling Over Four Conductors With Pre-Emphasis and Equalization: A CMOS Current Mode Implementation

机译：具有预加重和均衡功能的四个导体上的三数据差分信号：CMOS电流模式实现

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摘要

A current-mode differential signaling of three data over two pairs of transmission lines increases the effective maximum data rate per pair of transmission lines by about 37% over the conventional pure differential signaling. Each of two data is transmitted as a half-swing differential signal over a pair of transmission lines. The third data is transmitted as a half-swing complementary common-mode signal of the two pairs of transmission lines. Both a single-tap pre-emphasis and a single-tap decision feedback equalizer are combined with this work. Adding a D flip-flop between the equalizer amplifier and the MUX embedded D flip-flop of receiver enables 4-Gb/s operation of receiver. The chip fabricated by using a 0.25-μm CMOS process shows the maximum data rates of 4 and 3.2 Gb/s over 20- and 60-cm-long FR4 transmission lines, respectively, with bit-error rate below IE-12.
机译：两对传输线上的三个数据的电流模式差分信令比传统的纯差分信令将每对传输线的有效最大数据速率提高了约37％。两个数据中的每一个作为半摆幅差分信号通过一对传输线传输。第三数据作为两对传输线的半摆互补共模信号进行传输。单抽头预加重和单抽头决策反馈均衡器都与这项工作结合在一起。在均衡放大器和接收器的MUX嵌入式D触发器之间添加一个D触发器，可使接收器以4 Gb / s的速度工作。使用0.25μmCMOS工艺制造的芯片在20和60厘米长的FR4传输线上分别显示4和3.2 Gb / s的最大数据速率，误码率低于IE-12。

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