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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Analysis and Design of High-Performance Asynchronous Sigma-Delta Modulators With a Binary Quantizer
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Analysis and Design of High-Performance Asynchronous Sigma-Delta Modulators With a Binary Quantizer

机译：带有二进制量化器的高性能异步Sigma-Delta调制器的分析和设计

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Asynchronous sigma-delta modulators (ASDMs) are closed-loop nonlinear systems that transform the information in the amplitude of their input signal into time information in the output signal, without suffering from quantization noise such as in synchronous sigma-delta modulators. This is an important advantage with many interesting applications. In contrast with their synchronous counterparts, ASDMs have been underexposed. Both conceptually and analytically, they are quite complex. This paper investigates in detail the analysis, design and circuit-implementation aspects of ASDMs with a binary quantizer. In the ASDM, the amplitude-time transformation is done using an inherent self-oscillation denoted as a limit cycle. The oscillation frequency is addressed as the main design parameter that determines the spectral properties of the ASDMs and the quality of the amplitude-time transformation. Analytical and graphical derivations of the limit cycle frequency are treated. The impact of the filter order and the properties of the nonlinear element are elaborated on. Circuit implementations and the tradeoffs in the design are presented for a first- and a second-order ASDM that target the VDSL front-end specifications. Prototypes are implemented in a digital 0.18-μm 1.8-V CMOS technology. The measured SFDR is 75 dB in a frequency band of 8 MHz for the first-order ASDM, and 72 dB in a band of 12 MHz for the second-order ASDM. The dissipated power is 1.5 mW and 2.2 mW, respectively.
机译：异步sigma-delta调制器（ASDM）是一种闭环非线性系统，可将输入信号幅度中的信息转换为输出信号中的时间信息，而不会像同步sigma-delta调制器那样遭受量化噪声的影响。这是许多有趣应用程序的重要优势。与同步同步相比，ASDM曝光不足。在概念和分析上，它们都非常复杂。本文详细研究了具有二进制量化器的ASDM的分析，设计和电路实现方面。在ASDM中，使用表示为极限周期的固有自激振荡完成幅度-时间变换。振荡频率作为确定ASDM频谱特性和幅度时间转换质量的主要设计参数。处理极限循环频率的分析和图形推导。详细阐述了滤波器阶次的影响和非线性元件的特性。给出了针对VDSL前端规范的一阶和二阶ASDM的电路实现和设计中的折衷方案。原型以数字0.18μm1.8V CMOS技术实现。对于一阶ASDM，在8 MHz频带中测得的SFDR为75 dB，对于二阶ASDM，在12 MHz频带中测得的SFDR为72 dB。耗散功率分别为1.5 mW和2.2 mW。

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