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首页> 外文期刊>IEEE Journal of Solid-State Circuits >The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process
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The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process

机译:首款采用90nm数字CMOS工艺的全集成四频GSM / GPRS接收器

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摘要

We present the receiver in the first single-chip GSM/GPRS transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90-nm digital CMOS process. The architecture uses Nyquist rate direct RF sampling in the receiver and an all-digital phase-locked loop (PLL) for generating the local oscillator (LO). The receive chain uses discrete-time analog signal processing to down-convert, down-sample, filter and analog-to-digital convert the received signal. A feedback loop is provided at the mixer output and can be used to cancel DC-offsets as well to study linearization of the receive chain. The receiver meets a sensitivity of -110 dBm at 60 mA in a 1.4-V digital CMOS process in the presence of more than one million digital gates.
机译:我们在第一款单芯片GSM / GPRS收发器中展示了该接收器,该收发器在90纳米数字CMOS工艺中实现了四波段接收器,发射器,存储器,电源管理,专用ARM处理器和RF内置自测的完全集成。该架构在接收器中使用奈奎斯特速率直接RF采样以及用于生成本地振荡器(LO)的全数字锁相环(PLL)。接收链使用离散时间模拟信号处理来对接收到的信号进行下变频,下采样,滤波和模数转换。在混频器输出端提供了一个反馈环路,该反馈环路可用于消除直流偏移,还可以研究接收链的线性化。在存在超过一百万个数字门的情况下,在1.4V数字CMOS工艺中,接收器在60 mA时的灵敏度达到-110 dBm。

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