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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Dual-Modulus 127/128 FOM Enhanced Prescaler Design in 0.35-μm CMOS Technology
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Dual-Modulus 127/128 FOM Enhanced Prescaler Design in 0.35-μm CMOS Technology

机译：采用0.35-μmCMOS技术的双模127/128 FOM增强型预分频器设计

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摘要

The dual-modulus prescaler is a critical block in CMOS systems like high-speed frequency synthesizers. However, the design of high-moduli, high-speed, and low-power dual-modulus prescalers remains a challenge. To face the challenge, this paper introduces the idea of using transmission gates and pseudo-PMOS logic to realize the dual-modulus prescaler. The topology of the prescaler proposed is different from prior designs primarily in two ways: 1) it uses transmission gates in the critical path and 2) the D flip-flops (DFFs) used in the synchronous counter comprise pseudo-PMOS inverters and ratioed latches. A pseudo-PMOS logic-based DFF is introduced and used in the proposed prescaler design. Based on the proposed topology, a dual-modulus divide-by-127/128 prescaler is implemented in 0.35-μm CMOS technology. It consumes 4.8 mW from a 3-V supply. The measured phase noise is -143.4 dBc/Hz at 600 kHz. The silicon area required is only 0.06 mm{sup}2. There are no flip flops or logic gates in the critical path. This topology is suitable for high-speed and high-moduli prescaler designs. It reduces: 1) design complexity; 2) power consumption; and 3) input loading. Measurement results are provided. An improvement in the figure of merit is shown.
机译：双模预分频器是CMOS系统（如高速频率合成器）中的关键模块。但是，高模数，高速和低功率双模数预分频器的设计仍然是一个挑战。面对挑战，本文介绍了使用传输门和伪PMOS逻辑来实现双模预分频器的想法。所建议的预分频器的拓扑结构与现有设计的不同之处主要在于两个方面：1）它在关键路径中使用传输门； 2）同步计数器中使用的D触发器（DFF）包括伪PMOS反相器和比例锁存器。引入了基于伪PMOS逻辑的DFF，并将其用于建议的预分频器设计中。基于提出的拓扑，在0.35μmCMOS技术中实现了双模除以127/128的预分频器。 3V电源消耗的功率为4.8mW。在600 kHz时测得的相位噪声为-143.4 dBc / Hz。所需的硅面积仅为0.06 mm {sup} 2。关键路径中没有触发器或逻辑门。该拓扑适用于高速和高模数的预分频器设计。它降低了：1）设计复杂度； 2）功耗； 3）输入加载。提供了测量结果。显示了品质因数的改进。

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