Transistor and Circuit Design for 100-200-GHz ICs

Zach Griffith; Yingda Dong; Dennis Scott; Yun Wei; Navin Parthasarathy; Mattias Dahlstrom; Christoph Kadow; Vamsi Paidi; Mark J. W. Rodwell; Miguel Urteaga; Richard Pierson; Petra Rowell; Bobby Brar; Sangmin Lee; Nguyen X. Nguyen; Chahn Nguyen

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Transistor and Circuit Design for 100-200-GHz ICs

机译：100-200GHz IC的晶体管和电路设计

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Compared to SiGe, InP HBTs offer superior electron transport properties but inferior scaling and parasitic reduction. Figures of merit for mixed-signal ICs are developed and HBT scaling laws introduced. Device and circuit results are summarized, including a simultaneous 450 GHz f{sub}τ and 490 GHz f{sub}max DHBT, 172-GHz amplifiers with 8.3-dBm output power and 4.5-dB associated power gain, and 150-GHz static frequency dividers (a digital circuit figure-of-merit for a device technology). To compete with advanced 100-nm SiGe processes, InP HBTs must be similarly scaled and high process yields are imperative. Described are several process modules in development: these include an emitter-base dielectric sidewall spacer for increased yield, a collector pedestal implant for reduced extrinsic C{sub}(cb), and emitter junction regrowth for reduced base and emitter resistances.

机译：与SiGe相比，InP HBT具有出色的电子传输性能，但缩放性和寄生减少性却较差。制定了混合信号IC的品质因数，并引入了HBT缩放定律。总结了设备和电路的结果，包括同时进行的450 GHz fDH和490 GHz fmax DHBT，具有8.3dBm输出功率和4.5dB相关功率增益的172GHz放大器以及150GHz静态分频器（设备技术的数字电路品质因数）。为了与先进的100 nm SiGe工艺竞争，InP HBT必须进行类似的缩放，并且必须实现高工艺良率。描述中的几个工艺模块正在开发中：这些模块包括一个用于提高产量的发射极-基极电介质侧壁间隔物，一个用于降低非本征C {sub}（cb）的集电极基座植入物，以及一个用于降低基极和发射极电阻的发射极结长。

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来源
《IEEE Journal of Solid-State Circuits》 |2005年第10期|p.2061-2069|共9页
作者
Zach Griffith; Yingda Dong; Dennis Scott; Yun Wei; Navin Parthasarathy; Mattias Dahlstrom; Christoph Kadow; Vamsi Paidi; Mark J. W. Rodwell; Miguel Urteaga; Richard Pierson; Petra Rowell; Bobby Brar; Sangmin Lee; Nguyen X. Nguyen; Chahn Nguyen;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
InP heterojunction bipolar transistor; Static frequency divider; Millimeter-wave amplifier; Dielectric side-wall-spacer; Collector pedestal; Emitter regrowth;

机译：InP异质结双极晶体管;静态分频器;毫米波放大器;介电侧壁-间隔器;集电极基座;发射极长;

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1. Discussion on ????????Junction-transistor bootstrap linear-sweep circuits????????, ????????Design considerations of junction-transistor oscillators for the conversion of power from direct to alternating current???????? and ????????Minority-carrier storage in semi-conductor diodes???????? before the Radio and Telecommunication Section, 23rd January, 1957 [J] . Proceedings of the IEE - Part B: Radio and Electronic Engineering . 1957,第15期

机译：关于结型晶体管自举线性扫描电路的讨论结型晶体管振荡器在将功率从直接转换为功率时的设计考虑交流电?????????半导体载流子中的少数载流子存储1957年1月23日在无线电和电信科之前
2. Discussion on ????????The application of transistors to the trigger, ratemeter and power-supply circuits of radiation monitors????????, ????????A point-contact transistor scaling circuit with 0.4 microsec resolution???????? and ????????A junction-transistor scaling circuit with 2 microsec resolution???????? before the joint meeting of the Measurement and Control Section and the Radio and Telecommunication Section, 27th March, 1956 [J] . Proceedings of the IEE - Part B: Radio and Electronic Engineering . 1956,第10期

机译：讨论晶体管在辐射监测器的触发，速率计和电源电路中的应用?????????，点接触晶体管的定标分辨率为0.4微秒的电路以及具有2微秒分辨率的结型晶体管缩放电路。 1956年3月27日，在测控科和无线电与电信科的联席会议之前
3. The authors' reply to the discussion on ????????The application of transistors to the trigger, ratemeter and power-supply circuits of radiation monitors????????, ????????A point-contact transistor scaling circuit with 0.4 microsec resolution???????? and ????????A junction-transistor scaling circuit with 2 microsec resolution???????? [J] . Franklin E., James J.B., Chaplin G.B.B., Proceedings of the IEE - Part B: Radio and Electronic Engineering . 1956,第10期

机译：作者对有关晶体管在辐射监测器的触发，速率计和电源电路中的应用的讨论的答复。具有0.4微秒分辨率的点接触式晶体管缩放电路以及具有2微秒分辨率的结型晶体管缩放电路。
4. Device Physics and Design Theory of Si, Ge and Si1-xGex Vertical Dual Carrier Field Effect Transistor Integrated Circuits on Insulator with Effective Channel Length of 5-18nm [C] . 2006 8th International Conference on Solid-State and Integrated Circuit Technology(第八届国际固态和集成电路技术会议)论文集 . 2006

机译：绝缘体上有效沟道长度为5-18nm的Si，Ge和Si1-xGex垂直双载流子场效应晶体管集成电路的器件物理和设计理论
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7. A Practical Approach to Parasitic Extraction for Design of Multimillion-Transistor Integrated Circuits [O] . Eileen You, Lakshminarasimh Varadadesikan, John Macdonald, 2013

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8. Static and Dynamic Performance of Micropower Transistor Logic Circuits. Part II. Micropower Logic Circuit Design [R] . Wagner, L. F., Meindl, J. D. 1967

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Transistor and Circuit Design for 100-200-GHz ICs

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