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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector
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A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector

机译:具有健壮的锁定检测器的39至45Gbit / s多数据速率时钟和数据恢复电路

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摘要

We describe a 40-Gbit/s-class clock and data recovery (CDR) circuit with an extremely wide pull-in range. A Darlington-type voltage-controlled oscillator (VCO) is newly designed to cover the STM-256/OC-768 full-rate-clock frequencies with a wide frequency margin. We also describe a new lock detector using an exclusive-NOR gate. The CDR IC was fabricated using InP/InGaAs HBTs. Error-free operation and wide eye opening were confirmed for 40-, 43-, and 45-Gbit/s PRBS with a word length of 231 - 1. We attached a frequency search and phase control (FSPC) circuit to the chip as a new frequency acquisition aid, and this allows the CDR circuit to pull in throughout a 39-45-Gbit/s range. The peak-to-peak and rms jitter of the recovered clock were 3.6 and 0.48 ps, respectively.
机译:我们将介绍一个具有极宽输入范围的40 Gbit / s级时钟和数据恢复(CDR)电路。达林顿型压控振荡器(VCO)的最新设计可覆盖STM-256 / OC-768全速率时钟频率,并具有很大的频率裕量。我们还将介绍一种使用异或非门的新型锁定检测器。 CDR IC是使用InP / InGaAs HBT制造的。对于40G,43G和45Gbit / s的PRBS,字长为231-1。证实了其无差错操作和睁大眼睛的特性。我们将频率搜索和相位控制(FSPC)电路连接到芯片,作为新的频率采集辅助,这使CDR电路可在39-45Gbit / s的范围内接入。恢复时钟的峰峰值抖动和均方根抖动分别为3.6和0.48 ps。

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