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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Resonant clocking using distributed parasitic capacitance
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Resonant clocking using distributed parasitic capacitance

机译：使用分布式寄生电容的谐振时钟

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摘要

A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies. Theory predicts that the data passing though the clocked logic will change the clock frequency by less than 1.25%. A resonant clock test chip was designed and fabricated in an IBM 0.13-Μm partially depleted SOI process. Although the test chip was designed to operate in the gigahertz range using integrated inductors, startup difficulties required the addition of external inductance to reduce the resonant frequency so that the effects of the parasitic capacitance could be measured. The parasitic capacitance is approximately 40 pF per clock phase, resulting in a clock frequency between 106 and 146 MHz, depending on biasing. At its most efficient bias point, the clock dissipated 2.09 mW, which is approximately 35% less power than a conventional, buffer-driven clock. The maximum period jitter measured in the resonant clock due to changing data in the clocked latches was 55 ps at 124 MHz, or 0.68% of the clock period.
机译：描述了一种谐振时钟生成和分配方案，该方案使用时钟逻辑的固有寄生电容作为负电阻振荡器中的集总电容器。时钟能量在电感器和寄生本地时钟网络之间产生谐振，以节省传统时钟方法的功耗。理论预测，通过时钟逻辑的数据将使时钟频率变化小于1.25％。谐振时钟测试芯片是在IBM0.13-μm部分耗尽SOI工艺中设计和制造的。尽管测试芯片被设计为使用集成电感器在千兆赫兹范围内运行，但启动困难需要增加外部电感来降低谐振频率，以便可以测量寄生电容的影响。每个时钟相位的寄生电容约为40 pF，根据偏置的不同，时钟频率在106和146 MHz之间。在其最有效的偏置点，时钟耗散2.09 mW，比传统的缓冲器驱动时钟功耗低约35％。由于时钟锁存器中数据的变化，在谐振时钟中测得的最大周期抖动为55 ps（124 MHz），或时钟周期的0.68％。

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