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首页> 外文期刊>IEEE Journal of Solid-State Circuits >InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers
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InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

机译：InP HBT集成电路技术，具有选择性注入的子集电极和重新生长的器件层

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We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with ft>250 GHz and DHBT with ft>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.
机译：我们描述了使用带重新生长的MBE设备层的图案化植入子集电极的准平面HBT工艺。使用此过程，我们已经证明了ft> 250 GHz的离散SHBT和ft> 230 GHz的DHBT。该工艺消除了将基极电阻换为外部基极/集电极电容的需要。与标准台面器件相比，基极/集电极电容减小了2倍，重掺杂基极和子集电极区域之间完全重叠。低比例的非本征基极/集电极电容即使在深亚微米发射极中也能实现集电极的进一步垂直缩放，从而允许更高的电流密度工作。用这种工艺制造的演示环形振荡器具有出色的均匀性和良率，栅极延迟低至7 ps，功耗为6 mW / CML。在较低偏置电流下，功率延迟积低至20 fJ。据我们所知，这是在InP上使用图案化注入的高性能HBT和集成电路的首次演示。

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