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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps
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A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps

机译:使用两个开关运算放大器的1V 10.7 MHz四阶带通ΔΣ调制器

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A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-Μm 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.
机译:给出了使用两个开关运算放大器(SOP)的1V 10.7 MHz四阶带通Δ-Σ调制器。 3/4采样频率和双采样技术适用于此调制器,以放宽所需的时钟速率。提出的调制器不仅可以减少SOP的数量,而且可以减少电容器的数量。它已通过MIM电容器以0.25-μm1P5M CMOS工艺实现。调制器可以通过使用7.13 MHz的时钟频率来接收10.7 MHz的IF信号。在200 kHz带宽内实现了62 dB的动态范围,在1V电源电压下测得的功耗为8​​.45 mW。相对于载波,可以将图像色调抑制44 dB。带内三阶互调(IM3)失真比所需信号低-65 dBc。

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