...
  • 主题
高级搜索  >
历史搜索 清空历史
首页> 外文期刊>IEEE Journal of Solid-State Circuits >A continuous-time ΣΔ ADC with increased immunity to interferers
【24h】

A continuous-time ΣΔ ADC with increased immunity to interferers

机译：具有增强的抗干扰能力的连续时间ΣΔADC

获取原文
获取原文并翻译 | 示例
           
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Receivers are being digitized in a quest for flexibility. Analog filters and programmable gain stages are being exchanged for digital processing at the price of a very challenging ADC. This paper presents an alternative solution where the filter and programmable gain functionality is integrated into a ΣΔ ADC. The novel filtering ADC is realized by adding a high-pass feedback path to a conventional ΣΔ ADC while a compensating low-pass filter in the forward path maintains stability. As such, the ADC becomes highly immune to interferers even if they exceed the maximum allowable input level for the wanted channel. As a consequence, the ADC input range can be programmed dynamically to the level of the wanted signal only. This results in an input-referred dynamic range of 89 dB in 1-MHz bandwidth and an intentionally moderate output signal-to-noise-and-distortion ratio of 46-59 dB (depending on the programmed gain). The merged functionality enables a better overall power/performance balance for the receiver baseband. The design consumes less than 2 mW and active area is 0.14 mm2 in a 0.18-Μm digital CMOS technology.
机译：接收器正在数字化以寻求灵活性。模拟滤波器和可编程增益级正以具有挑战性的ADC的价格进行数字处理交换。本文提出了一种将滤波器和可编程增益功能集成到ΣΔADC中的替代解决方案。通过向传统的ΣΔADC添加高通反馈路径，同时在正向路径中的补偿低通滤波器保持稳定性，可以实现新颖的滤波ADC。这样，即使干扰信号超过了所需通道的最大允许输入电平，ADC也能高度不受干扰。结果，只能将ADC输入范围动态地编程为所需信号的电平。这导致在1-MHz带宽内具有89dB的输入参考动态范围，并且有意适度的46-59dB输出信噪比（取决于编程的增益）。合并的功能为接收机基带实现了更好的整体功率/性能平衡。采用0.18微米数字CMOS技术，该设计的功耗不到2 mW，有效面积为0.14 mm2。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号