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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A CMOS voltage reference based on weighted ΔVGS for CMOS low-dropout linear regulators
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A CMOS voltage reference based on weighted ΔVGS for CMOS low-dropout linear regulators

机译：基于加权ΔVGS的CMOS低压差线性稳压器的CMOS参考电压

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摘要

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-Μm CMOS technology (Vthn≈|Vthp|≈0.9 V at 0°C). The occupied chip area is 0.055 mm2. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 ΜA. A typical mean uncalibrated temperature coefficient of 36.9 ppm/°C is achieved, and the typical mean line regulation is ±0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV/√(Hz) and that at 100 kHz is 1.6 nV/√(Hz).
机译：提出了一种CMOS参考电压，该参考电压基于在饱和区工作的NMOST和PMOST的栅极-源极电压的加权差。参考电压是为CMOS低压差线性稳压器设计的，已在标准0.6μmCMOS技术中实现（0°C时Vthn≈| Vthp |≈0.9V）。占用的切屑面积为0.055 mm2。最小电源电压为1.4 V，最大电源电流为9.7ΜA。获得的典型平均未校准温度系数为36.9 ppm /°C，典型的平均线路调节度为±0.083％/ V。在没有任何滤波电容器的情况下，在100 Hz和10 MHz时的电源抑制比分别为-47和-20 dB。此外，使用100nF滤波电容器在100 Hz下测得的噪声密度为152 nV /√（Hz），在100 kHz下为1.6 nV /√（Hz）。

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