A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture

Miyazaki D.; Kawahito S.; Furuta M.

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A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture

机译：使用伪差分架构的10-b 30-MS / s低功耗流水线CMOS A / D转换器

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摘要

A 10-b 30-MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is described. The ADC using a pseudodifferential architecture and a capacitor cross-coupled sample-and-hold stage consumes 16 mW with a single 2-V supply. The chip is fabricated in a standard 0.3-/spl mu/m two-poly three-metal CMOS technology. The achieved low-power dissipation normalized by the sampling frequency of 0.52 mW/MHz is superior to other high-speed low-power ADCs reported. The ADC has a signal-to-noise-and-distortion ratio of 54 dB at an input frequency of 15 MHz. The maximum differential and integral nonlinearity are 0.4 and 0.5 LSB, respectively.

机译：描述了一种10b 30 MS / s低功耗CMOS流水线模数转换器（ADC）。采用伪差分架构和电容器交叉耦合采样保持级的ADC在2V单电源供电下的功耗为16mW。该芯片采用标准的0.3- / splμm/ m的两层三金属CMOS技术制造。通过0.52 mW / MHz的采样频率归一化实现的低功耗优于其他报道的高速低功耗ADC。 ADC在15 MHz的输入频率下具有54 dB的信噪比和失真比。最大微分和积分非线性分别为0.4和0.5 LSB。

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来源
《IEEE Journal of Solid-State Circuits》 |2003年第2期|p.369-373|共5页
作者
Miyazaki D.; Kawahito S.; Furuta M.;
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作者单位

Graduate Sch. of Electron. Sci. & Technol., Shizuoka Univ., Japan;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
low-power electronics; pipeline processing; analogue-digital conversion; CMOS integrated circuits; sample and hold circuits; CMOS A/D converter; low-power CMOS ADC; pipelined ADC; analog-to-digital converter; pseudodifferential architecture; capacito;

机译：低功耗电子产品;管道处理;模数转换;CMOS集成电路;采样和保持电路;CMOS A / D转换器低功耗CMOS ADC;流水线ADC;模数转换器;伪差分架构;卡帕西托;

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1. A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture [J] . Miyazaki D., Kawahito S., Furuta M. IEEE Journal of Solid-State Circuits . 2003,第2期

机译：使用伪差分架构的10-b 30-MS / s低功耗流水线CMOS A / D转换器
2. A 1.5 V 10-b 30-MS/s CMOS pipelined analog-to-digital converter [J] . Chi-Chang Lu Analog Integrated Circuits and Signal Processing . 2011,第3期

机译：1.5 V 10-b 30-MS / s CMOS流水线模数转换器
3. A 1.5 V 10-b 30-MS/s CMOS pipelined analog-to-digital converter [J] . Chi-Chang Lu Analog Integrated Circuits and Signal Processing . 2011,第3期

机译：1.5 V 10-b 30-MS / s CMOS流水线模数转换器
4. A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter [C] . Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee . 2007

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5. A 12-bit, 40 msamples/s, low-power, low-area pipeline analog-to-digital converter in CMOS 0.18 mum technology. [D] . Mohajerin, Mani. 2004

机译：采用CMOS 0.18毫米技术的12位，40 msamples / s，低功耗，低面积流水线模数转换器。
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7. Realization of Compact Low-Power Ripple-Flash A/D Converter Architectures Using Conventional Digital CMOS Technology [O] . Renato Baumgartner 2008

机译：利用传统数字CmOs技术实现紧凑型低功耗纹波闪存a / D转换器架构

A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture

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