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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology
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A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

机译：采用multi-V / sub / SOI CMOS技术的低功耗系统LSI的0.5V电源方案

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This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.
机译：本文提出了一种适用于0.5V操作绝缘体上硅（SOI）CMOS电路的新型电源方案。该系统包含一个效率超过90％的片上降压DC-DC转换器，0.5V工作逻辑电路，0.5V电源下的100MHz工作触发器以及用于0.5V之间接口的电平转换器操作电路和片上数模（D / A）转换器或外部设备。基于该理论，明确了0.5 V / 10 mW输出DC-DC转换器的SOI晶体管的导通电阻值和阈值电压，该值可同时满足高效率和低待机功耗的要求。所提出的触发器可以使用外部电源在睡眠期间保存数据，同时在有源期间保持高性能。电平转换器包括双轨电荷传输门和带有交叉耦合nMOS放大器的CMOS缓冲器，即使在转换增益高于6时也可以高速运行，其中转换增益定义为输出与输入之比信号摆动。通过使用multi-V / sub / SOI CMOS技术为0.5-V电源方案制造了测试芯片。实验结果表明，降压DC-DC转换器在0.5-V / 10-mW输出时实现了91％的转换效率，并具有从睡眠状态恢复的稳定特性，并且双轨电平转换器在最大数据传输速率为5％的条件下工作。 300 Mb / s，输入信号摆幅为0.5V。

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