A fast locking and low jitter delay-locked loop using DHDL

Hsiang-Hui Chang; Jyh-Woei Lin; Shen-Iuan Liu

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A fast locking and low jitter delay-locked loop using DHDL

机译：使用DHDL的快速锁定和低抖动延迟锁定环路

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摘要

A fast-locking and low-jitter delay-locked loop (DLL) using the digital-controlled half-replica delay line (DHDL) is presented. The DHDL can provide stable bias voltage for the charge-pump circuit to achieve low-jitter performances; meanwhile, the property of bandwidth tracking can still be preserved. It can also provide a larger pumping current to reduce the lock time in the initialization state and provide a smaller current to improve jitter performance in the locked state. For comparisons, both the proposed DLL and the self-biased DLL have been fabricated in a 0.35-/spl mu/m one-poly four-metal CMOS process. From the measurement results, the proposed DLL has a shorter lock time and a better jitter performance than the self-biased DLL. The root-mean-squared jitter and peak-to-peak jitter are less than 4.2 and 30 ps, respectively, occurring at 75 MHz, over an operating frequency range of 50-150 MHz.

机译：提出了一种使用数字控制的半复制延迟线（DHDL）的快速锁定和低抖动延迟锁定环（DLL）。 DHDL可以为电荷泵电路提供稳定的偏置电压，以实现低抖动性能。同时，仍然可以保留带宽跟踪的属性。它还可以提供较大的泵浦电流以减少初始化状态下的锁定时间，并提供较小的电流以改善锁定状态下的抖动性能。为了进行比较，建议的DLL和自偏置DLL均以0.35- / splμu/ m的单层四金属CMOS工艺制造。从测量结果来看，所提出的DLL比自偏置DLL具有更短的锁定时间和更好的抖动性能。在50-150 MHz的工作频率范围内，均方根抖动和峰峰值抖动分别小于75 MHz的4.2 ps和30 ps。

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来源
《IEEE Journal of Solid-State Circuits》 |2003年第2期|p.343-346|共4页
作者
Hsiang-Hui Chang; Jyh-Woei Lin; Shen-Iuan Liu;
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作者单位

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
CMOS integrated circuits; delay lock loops; mixed analogue-digital integrated circuits; delay lines; jitter; fast-locking DLL; low-jitter DLL; delay-locked loop; analog DLL; digital-controlled half-replica delay line; stable bias voltage; charge-pump;

机译：CMOS集成电路;延迟锁定循环;混合模数集成电路;延迟线;抖动快速锁定的DLL;低抖动DLL;延迟锁定环;模拟DLL;数控半复制延迟线;稳定的偏压;电荷泵;

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专利

1. A fast locking and low jitter delay-locked loop using DHDL [J] . Hsiang-Hui Chang, Jyh-Woei Lin, Shen-Iuan Liu IEEE Journal of Solid-State Circuits . 2003,第2期

机译：使用DHDL的快速锁定和低抖动延迟锁定环路
2. A multi-band fast-locking delay-locked loop with jitter-bounded feature [J] . Chien-Hung Kuo, Hung-Jing Lai, Meng-Feng Lin Ultrasonics, Ferroelectrics and Frequency Control, IEEE Transactions on . 2011,第1期

机译：具有抖动限制功能的多频段快速锁定延迟锁定环路
3. Analysis and design of a low jitter delay-locked loop using lock state detector [J] . Modanlou Shahram, Ardeshir Gholamreza, Gholami Mohammad International journal of circuit theory and applications . 2021,第5期

机译：锁定状态检测器的低抖动延迟锁环的分析与设计
4. A multi-band delay-locked loop with fast-locked and jitter-bounded features [C] . Kuo Chien-Hung, Meng-Feng Lin, Chen Chien-Hung IEEE Asian Solid-State Circuits Conference . 2008

机译：具有快速锁定和抖动界限功能的多频段延迟锁环
5. Research and design of low jitter, wide locking-range all-digital phase-locked and delay-locked loops. [D] . Lin, Feng. 2000

机译：低抖动，宽锁定范围全数字锁相环和延迟锁相环的研究和设计。
6. Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications [O] . Bilal I. Abdulrazzaq, Omar J. Ibrahim, Shoji Kawahito, 2016

机译：具有可调范围CMOS延迟锁定环路的亚皮秒抖动设计适用于高速和低功耗应用
7. Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications [O] . Bilal I. Abdulrazzaq, Omar J. Ibrahim, Shoji Kawahito, 2016

机译：具有可调范围CmOs延迟锁定环的亚皮秒抖动设计，适用于高速和低功耗应用

A fast locking and low jitter delay-locked loop using DHDL

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