A 2-V 23-/spl mu/A 5.3-ppm//spl deg/C curvature-compensated CMOS bandgap voltage reference

Ka Nang Leung; Mok P.K.T.; Chi Yat Leung

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A 2-V 23-/spl mu/A 5.3-ppm//spl deg/C curvature-compensated CMOS bandgap voltage reference

机译：2 V 23- / splμ/ A 5.3-ppm // spl deg / C曲率补偿CMOS带隙电压基准

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摘要

A high-order curvature-compensated CMOS bandgap reference, which utilizes a temperature-dependent resistor ratio generated by a high-resistive poly resistor and a diffusion resistor, is presented in this paper. Implemented in a standard 0.6-/spl mu/m CMOS technology with V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C, the proposed voltage reference can operate down to a 2-V supply and consumes a maximum supply current of 23 /spl mu/A. A temperature coefficient of 5.3 ppm//spl deg/C at a 2-V supply and a line regulation of /spl plusmn/1.43 mV/V at 27/spl deg/C are achieved. Experimental results show that the temperature drift is reduced by approximately five times when compared with a conventional bandgap reference in the same technology.

机译：本文提出了一种高阶曲率补偿CMOS带隙基准，该基准利用了由高电阻多晶硅电阻和扩散电阻产生的温度相关电阻比。以标准的0.6- / spl mu / m CMOS技术实现，电压为0 / spl deg / C时，V / sub thn // spl ap / | V / sub thp / | / spl ap / 0.9 V降低至2V电源，消耗的最大电源电流为23 / spl mu / A。在2V电源下的温度系数为5.3 ppm // spl deg / C，在27 / spl deg / C的条件下，线调节达到/ spl plusmn / 1.43 mV / V。实验结果表明，与相同技术中的常规带隙基准相比，温度漂移降低了大约五倍。

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来源
《IEEE Journal of Solid-State Circuits》 |2003年第3期|p.561-564|共4页
作者
Ka Nang Leung; Mok P.K.T.; Chi Yat Leung;
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作者单位

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
compensation; reference circuits; CMOS integrated circuits; low-power electronics; curvature-compensated reference; CMOS; bandgap voltage reference; low-voltage applications; temperature-dependent resistor ratio; high-resistive poly resistor; diffusi;

机译：赔偿;参考电路;CMOS集成电路;低功耗电子产品;曲率补偿参考;CMOS;带隙基准电压;低压应用;与温度有关的电阻比;高阻多晶硅电阻器;弥漫性;

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专利

1. A 2-V 23-ΜA 5.3-ppm/°C curvature-compensated CMOS bandgap voltage reference [J] . Ka Nang Leung, Mok P.K.T., Chi Yat Leung IEEE Journal of Solid-State Circuits . 2003,第3期

机译：2V23-ΜA5.3-ppm /°C曲率补偿CMOS带隙基准电压源
2. Accurate low power bandgap voltage reference in 0.5 /spl mu/m CMOS technology [J] . Sanduleanu M.A.T., Van Tuijl A.J.M. Electronics Letters . 1998,第10期

机译：0.5 / splμm/ m CMOS技术中的精确低功耗带隙基准电压源
3. A CMOS 4.6ppm/°C curvature-compensated bandgap voltage reference [J] . Huaxi Gu, Lianxi Liu, Minjie Liu, IEICE Electronics Express . 2012,第20期

机译：CMOS 4.6ppm /°C曲率补偿带隙基准电压源
4. A 2-V 23-/spl mu/ 5.3-ppm//spl deg/C 4th-order curvature-compensated CMOS bandgap reference [C] . Ka Nang Leung, Mok, P.K.T., . 2002

机译：2 V 23- / spl mu / 5.3-ppm // spl deg / C 4阶曲率补偿CMOS带隙基准
5. An accurate, trimless, high PSRR, low-voltage, CMOS bandgap reference IC. [D] . Gupta, Vishal. 2007

机译：一款精确，无扰动，高PSRR，低压，CMOS带隙基准IC。
6. Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference [O] . El Hafed Boufouss, Laurent A. Francis, Valeriya Kilchytska, 2013

机译：超低功率高温和辐射硬互补金属氧化物半导体（CMOS）绝缘体上硅（SOI）电压基准
7. A 3 V 110 μW 3.1 ppm/°C curvature-compensated CMOS bandgap reference [O] . Xiaokang Guan, Xin Wang, Albert Wang, 2009

机译：3 V 110μW3.1 ppm /°C曲率补偿CMOS带隙基准

A 2-V 23-/spl mu/A 5.3-ppm//spl deg/C curvature-compensated CMOS bandgap voltage reference

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