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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Jitter transfer characteristics of delay-locked loops - theories and design techniques
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Jitter transfer characteristics of delay-locked loops - theories and design techniques

机译：延迟锁定环路的抖动传递特性-理论和设计技术

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摘要

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a z-domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a first-order DLL and an overdamped second-order DLL. The amount of jitter peaking is shown to trade off with the tracking bandwidth and, therefore, the acquisition time. Techniques to reduce jitter amplification by loop filtering and phase filtering are discussed. Measurements from a prototype chip incorporating the discussed techniques confirm the prediction of the analytical model. In environments where the reference clock is noisy or where multiple timing circuits are cascaded, this jitter amplification effect should be carefully evaluated.
机译：本文介绍了延迟锁定环路（DLL）的抖动传递的分析和实验结果。通过z域模型，我们显示出在广泛使用的DLL配置中，抖动峰值始终存在，并且高频抖动不会像以前的分析所表明的那样衰减。即使在一阶DLL和过阻尼的二阶DLL中也是如此。抖动峰值的量显示为与跟踪带宽和因此的采集时间权衡。讨论了通过环路滤波和相位滤波来减少抖动放大的技术。结合讨论的技术的原型芯片的测量结果证实了分析模型的预测。在基准时钟噪声较大或多个定时电路级联的环境中，应仔细评估这种抖动放大效果。

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