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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A low-power ROM using charge recycling and charge sharing techniques
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A low-power ROM using charge recycling and charge sharing techniques

机译：使用电荷回收和电荷共享技术的低功耗ROM

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摘要

In a memory, most power is dissipated in high-capacitive lines such as predecoder lines, wordlines, and bitlines. To reduce the power dissipation in these high-capacitive lines, this paper proposes three techniques using charge recycling and charge sharing. The first is the charge recycling predecoder (CRPD), the second is the charge recycling wordline decoder (CRWD), and the last one is the charge sharing bitline (CSBL) for a ROM. The CRPD and the CRWD recycle the previously used charge in predecoder lines and wordlines. Theoretically, the power consumption in predecoder lines and wordlines are reduced to a half. The CSBL reduces the swing voltage in the ROM bitlines to very small voltage using a charge sharing technique with three small capacitors. The CSBL can significantly reduce the power dissipation in ROM bitlines. The CRPD, the CRWD, and the CSBL consume 82%, 72%, and 64%, respectively, of the power of previous ROM designs. A charge recycling and charge sharing ROM (CRCS-ROM) with the CRPD, the CRWD, and the CSBL is implemented. A CRCS-ROM with 8K /spl times/ 16 bits was fabricated in a 0.35-/spl mu/m CMOS process. The CRCS-ROM consumes 8.63 mW at 100 MHz with 3.3 V. The chip core area is 0.51 mm/sup 2/.
机译：在存储器中，大部分功率消耗在高电容线中，例如预解码器线，字线和位线。为了减少这些高电容线路的功耗，本文提出了三种使用电荷回收和电荷共享的技术。第一个是电荷回收预解码器（CRPD），第二个是电荷回收字线解码器（CRWD），最后一个是ROM的电荷共享位线（CSBL）。 CRPD和CRWD在预解码器线和字线中回收先前使用的电荷。从理论上讲，预解码器线和字线中的功耗降低了一半。 CSBL使用带有三个小电容器的电荷共享技术将ROM位线中的摆幅电压减小到很小的电压。 CSBL可以大大减少ROM位线的功耗。 CRPD，CRWD和CSBL分别消耗了先前ROM设计功耗的82％，72％和64％。实现了与CRPD，CRWD和CSBL的电荷回收和电荷共享ROM（CRCS-ROM）。以0.35- / spl mu / m CMOS工艺制造了具有8K / spl次/ 16位的CRCS-ROM。 CRCS-ROM在100 MHz和3.3 V时消耗8.63 mW。芯片核心面积为0.51 mm / sup 2 /。

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