Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz

Schuster S.E.; Cook P.W.

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Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz

机译：工作在3.3-4.5 GHz的低功耗同步到异步互锁流水线CMOS电路

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Interlocked pipelined CMOS (IPCMOS), a new asynchronous set of clock circuits suitable for high-frequency and low-power operation, is described. In IPCMOS, the reduced power results from enabling the local clocks only when there is an operation to perform and from a simple single-stage latch. The single-stage latch can be used because the locally generated clocks driving adjacent stages are not enabled simultaneously. The combination of enabling the clocks only when there is an operation to perform and the simple latch can lower power by a factor of five to ten times in many applications. In IPCMOS, the staggered local clocks also result in a significant reduction of dynamic Ldi/dt noise. In addition to the locally generated interlocked clocks and the single-stage latch, unique circuits that combine the function of a static NOR and an input switch are key to achieving high performance and minimizing the overhead in the interlocking. In a 0.18-Μm bulk CMOS technology, these circuits drive a path through a typical 64-b multiplier stage at 3.3-4.5 GHz on an experimental chip. IPCMOS also provides a way to implement the interface between asynchronous and synchronous portions of a design, thereby giving the approach a great deal of flexibility by making it possible to drop IPCMOS into portions of an existing synchronous design.

机译：描述了互锁的流水线CMOS（IPCMOS），这是一组适用于高频和低功率操作的新的异步时钟电路。在IPCMOS中，功耗降低是由于仅在有操作要执行时才启用本地时钟，以及简单的单级锁存器。可以使用单级锁存器，因为无法同时启用驱动相邻级的本地生成时钟。在许多应用中，只有在有操作要执行时才启用时钟以及简单的锁存器的组合可以将功耗降低五到十倍。在IPCMOS中，交错的本地时钟还可以大大降低动态Ldi / dt噪声。除了本地生成的互锁时钟和单级锁存器之外，结合静态NOR和输入开关功能的独特电路对于实现高性能并最大程度地减少互锁的开销至关重要。在0.18μm体CMOS技术中，这些电路在实验芯片上驱动通过3.3-4.5 GHz的典型64-b乘法器级的路径。 IPCMOS还提供了一种在设计的异步和同步部分之间实现接口的方法，从而可以通过将IPCMOS放入现有同步设计的各个部分中，从而为该方法提供了很大的灵活性。

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来源
《IEEE Journal of Solid-State Circuits》 |2003年第4期|p.622-630|共9页
作者
Schuster S.E.; Cook P.W.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CMOS logic circuits; asynchronous circuits; clocks; low-power electronics; multiplying circuits; pipeline processing; 0.18 micron; 3.3 to 4.5 GHz; 64 bit; IPCMOS; clock circuits; high-frequency operation; interlocked pipelined CMOS circuits; local clocks; locally gene;

机译：CMOS逻辑电路;异步电路;时钟;低功耗电子设备;乘法电路;流水线处理;0.18微米;3.3至4.5 GHz;64位;IPCMOS;时钟电路;高频操作;互锁的流水线CMOS电路;本地时钟;本地基因;

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Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz

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