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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 2.4-GHz 0.18-/spl mu/m CMOS self-biased cascode power amplifier
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A 2.4-GHz 0.18-/spl mu/m CMOS self-biased cascode power amplifier

机译：一个2.4 GHz 0.18- / splμ/ m CMOS自偏置共源共栅功率放大器

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摘要

A two-stage self-biased cascode power amplifier in 0.18-/spl mu/m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8-2.4-GHz frequency range. A novel self-biasing and bootstrapping technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. The power amplifier shows no performance degradation after ten days of continuous operation under maximum output power at 2.4-V supply. It is demonstrated that a sliding bias technique can be used to both significantly improve the PAE at mid-power range and linearize the power amplifier. By using the sliding bias technique, the PAE at 16 dBm is increased from 6% to 19%, and the gain variation over the entire power range is reduced from 7 to 0.6 dB.
机译：提出了适用于Class-1蓝牙应用的0.18- / spl mu / m CMOS工艺的两级自偏置共源共栅功率放大器。功率放大器在2.4 GHz时可提供23 dBm的输出功率和42％的功率附加效率（PAE）。在饱和时，它具有38 dB的小信号增益和31 dB的大信号增益。这是在0.8-2.4 GHz频率范围内采用CMOS进行两阶段设计时报告的最高增益。提出了一种新颖的自偏置和自举技术，该技术可放宽功率放大器中因热载流子退化而引起的限制，并减轻了使用与相同工艺中的标准晶体管相比射频性能较差的厚氧化物晶体管的需求。在2.4V电源的最大输出功率下，连续运行十天后，功率放大器不会出现性能下降。事实证明，可以使用滑动偏置技术来显着改善中功率范围的PAE并使功率放大器线性化。通过使用滑动偏置技术，16 dBm时的PAE从6％增加到19％，并且整个功率范围内的增益变化从7 dB减小到0.6 dB。

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