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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A power-efficient wide-range phase-locked loop
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A power-efficient wide-range phase-locked loop

机译：高效节能的宽范围锁相环

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This work presents a phase-locked loop for clock generation thatnconsists of a phase/frequency detector, charge pump, loop filter,nrange-programmable voltage-controlled ring oscillator, and programmablendivider. The phase/frequency detector and charge pump are designed tonreduce the dead zone and charge sharing for enhancing the lockingnperformance, respectively. In the design of the range-programmablenvoltage-controlled oscillator, the original inverter ring of a delaynline is divided into several smaller ones, and then they are recombinednin parallel to each other. Programming the number of paralleled inverternrings allows us to generate the wide-range clock frequencies. Thisndesign shuts off some inverters that are not in use to reduce powernconsumption. To allow the phase-locked loop to shut off inverters, thenfeasibility of using controllable inverters by the output-switch andnpower-switch schemes is explored. Theoretical analyses indicate thatnpower consumption of the voltage-controlled oscillator depends onntransistors' sizes rather than operating frequencies. By applying thenTSMC 0.35-Μm CMOS technology, the proposed phase-locked loop thatnuses the power-switch scheme can yield clock signals ranging from 103nMHz to 1.02 GHz at a supply voltage of 1.8 V. Moreover, powerndissipation that is proportional to the number of paralleled inverternrings is measured with 1.32 to 4.59 mW. The phase-locked loop proposednherein can be used in various digital systems, providing power-efficientnand wide-range clock signals for task-oriented computations
机译：这项工作提出了一个用于时钟生成的锁相环，它由相位/频率检测器，电荷泵，环路滤波器，可程控电压控制的环形振荡器和可编程分频器组成。相位/频率检测器和电荷泵的设计分别减少了死区和电荷共享，以增强锁定性能。在范围可编程的压控振荡器的设计中，将延迟线的原始反相器环分成几个较小的环，然后将它们彼此并联重组。对并联的反相器nrings的数量进行编程可以使我们生成宽范围的时钟频率。此设计会关闭一些未使用的逆变器，以降低功耗。为了允许锁相环关闭逆变器，然后探讨了通过输出开关和n功率开关方案使用可控逆变器的可行性。理论分析表明，压控振荡器的功耗取决于晶体管的尺寸而不是工作频率。通过应用TSMC0.35-μmCMOS技术，所提议的锁相环在电源电压为1.8 V时可产生功率开关方案，可产生103nMHz至1.02 GHz的时钟信号。此外，与并联数量成正比的功率损耗逆变器环的功耗为1.32至4.59 mW。本文提出的锁相环可用于各种数字系统，为面向任务的计算提供高能效和宽范围的时钟信号

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