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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A CMOS transceiver for DRAM bus system with a demultiplexedequalization scheme
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A CMOS transceiver for DRAM bus system with a demultiplexedequalization scheme

机译：具有解复用均衡方案的DRAM总线系统的CMOS收发器

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摘要

An equalizing transceiver was implemented by using a 0.35-ΜmnCMOS technology for DRAM bus system. An equalization scheme was used innthe receiver to reduce intersymbol interference (ISI). To maximize thendata rate, a one-to-eight demultiplexing scheme was used in thenequalizer of the receiver such that eight equalizers operate in parallelnat the clock frequency, which is one-eighth the data rate. The maximumndata rates were measured to be 840 Mb/s with twelve 5-pF capacitorsnconnected in uniform spacing along a transmission line. The testncriterion for successive transmission was set to the bit-error raten(BER) of 10-12 for the pseudorandom binary sequence (PRBS)ndata. The effectiveness of equalizers was demonstrated by measuring thenBER with equalizers on and off, respectively. The chip size wasn800×400 Μm2 and the supply voltage was 3.3 V
机译：通过将0.35-ΜmnCMOS技术用于DRAM总线系统来实现均衡收发器。接收机中使用了一种均衡方案来减少符号间干扰（ISI）。为了使数据速率最大化，在接收机的均衡器中使用了一个八分之一的解复用方案，以使八个均衡器与时钟频率并行工作，时钟频率是数据速率的八分之一。沿着传输线以均匀间隔连接的十二个5-pF电容器n测得的最大数据速率为840 Mb / s。对于伪随机二进制序列（PRBS）ndata，将连续传输的标准设置为10-12的误码率n（BER）。通过分别在开启和关闭均衡器的情况下测量BER证明了均衡器的有效性。芯片尺寸为800×400μm2，电源电压为3.3 V

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