Compact associative-memory architecture with fully parallel searchcapability for the minimum Hamming distance

Mattausch H.J.; Gyohten T.; Soda Y.; Koide T.

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Compact associative-memory architecture with fully parallel searchcapability for the minimum Hamming distance

机译：紧凑的关联存储器架构，具有完全并行的搜索能力，可实现最小汉明距离

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An associative-memory architecture for a fully parallel minimumnHamming distance search is proposed, which uses digital circuitry fornbit comparison and fast analog circuitry for word comparison as well asnwinner-take-all (WTA) functionality. Following this original approachnallows compact and high-performance integration in conventional CMOSntechnology. First, static encoding of word-comparison results as ancurrent-sink capability reduces word-comparison circuitry to thentheoretical minimum, namely, one transistor per bit and one signal linenper word. Second, a new WTA principle, which we call self-adaptingnwinner line-up amplification (WLA), regulates the winner row outputnautomatically into the narrow maximum-gain region of a distancenamplifier. Third, winner search circuit complexity scales linear withnreference-word number and not quadratic as inevitable for digitalnapproaches. Due to static distance encoding and WLA regulation,ntransient noise and fabrication process variations are largelyntolerated. Only relative chip-internal transistor-parameter variations,ncreating effective mismatch of matched transistors, limit winner searchnresult correctness. Practical feasibility is verified

机译：提出了一种用于完全并行的最小汉明距离搜索的关联存储器体系结构，该体系结构使用数字电路进行位比较和快速模拟电路进行字比较以及“赢家通吃”（WTA）功能。遵循这种原始方法，可以在常规CMOSn技术中实现紧凑而高性能的集成。首先，字比较的结果是静态编码，因为电流吸收能力使字比较电路降至理论上的最小值，即每位一个晶体管，每个字一个信号线。其次，一种新的WTA原理（我们称为自适应赢家排队放大（WLA））将自动输出的赢家行调节到距离放大器的狭窄最大增益区域中。第三，获胜者搜索电路的复杂度与参考词的数量成线性比例，而不是数字化方法不可避免的二次方。由于静态距离编码和WLA规定，非瞬态噪声和制造工艺变化在很大程度上被消除。仅芯片内部晶体管的相对参数变化，造成匹配晶体管的有效失配，限制了获胜者搜索结果的正确性。实际可行性经过验证

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来源
《IEEE Journal of Solid-State Circuits》 |2002年第2期|p.218-227|共10页
作者
Mattausch H.J.; Gyohten T.; Soda Y.; Koide T.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CMOS memory circuits; Hamming codes; content-addressable storage; integrated circuit noise; mixed analogue-digital integrated circuits; CMOS; associative-memory architecture; bit comparison; current-sink capability; fabrication process variations; fully parallel s;

机译：CMOS存储电路;汉明码;内容可寻址存储;集成电路噪声;混合模数集成电路;CMOS;关联存储器架构;位比较;电流吸收能力;制造工艺变化;完全并行;

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专利

1. Architecture for compact and fast associative-memories with All-parallel nearest-match hamming-distance search [J] . Tetsushi Koide, Takayuki Gyohten, Yoshihiro Soda, 電子情報通信学会技術研究報告. 集積回路. Integrated Circuits and Devices . 2001,第1期

机译：具有全并行最近匹配汉明距离搜索的紧凑而快速的关联存储器的体系结构
2. Architecture for compact and fast associative-memories with All-parallel nearest-match hamming-distance search [J] . Tetsushi Koide, Takayuki Gyohten, Yoshihiro Soda, 電子情報通信学会技術研究報告. 集積回路. Integrated Circuits and Devices . 2001,第1期

机译：紧凑型和快速关联回忆的架构，具有全平行的最近匹配的汉明远程搜索
3. A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture [J] . Oike Y., Ikeda M., Asada K. IEEE Journal of Solid-State Circuits . 2004,第8期

机译：使用字并行和分层搜索体系结构的具有精确汉明/曼哈顿距离估计的高速低压关联协处理器
4. A high-speed and low-voltage associative co-processor with Hamming distance ordering using word-parallel and hierarchical search architecture [C] . Oike, Y., Ikeda, . 2003

机译：汉明距离排序的高速低压关联协处理器，采用字并行和分层搜索架构
5. Hamming Distance Computation in Unreliable Resistive Memory [D] . Chen, Zehui. 2018

机译：不可靠电阻记忆中的汉明距离计算
6. Analysis of Solar Irradiation Time Series Complexity and Predictability by Combining Kolmogorov Measures and Hamming Distance for La Reunion (France) [O] . Dragutin T. Mihailović, Miloud Bessafi, Sara Marković, 2018

机译：Kolmogorov测量与La Reunion的汉敏距离与汉字距离相结合的太阳照射时间序列复杂性和可预测性分析
7. A high-speed and low-voltage associative co-processor with hamming distance ordering using word-parallel and hierarchical search architecture [O] . Yusuke Oike, Student Member, Makoto Ikeda, 2015

机译：具有汉明距离排序的高速和低压关联协处理器，使用字并行和分层搜索架构

Compact associative-memory architecture with fully parallel searchcapability for the minimum Hamming distance

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