Switched-current circuits in digital CMOS technology with low charge-injection errors

Balachandran G.K.; Allen P.E.

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Switched-current circuits in digital CMOS technology with low charge-injection errors

机译：具有低电荷注入误差的数字CMOS技术中的开关电流电路

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In this paper, digital CMOS switched-current (SI) circuits with low charge-injection errors are presented. These circuits are based on the operation of the switches at virtual-ground nodes to result in signal-independent charge injection. Based on this scheme, different topologies for the memory cell are discussed. To verify the theoretical concepts developed, a third-order elliptic low-pass SI filter is implemented in a 0.25-/spl mu/m digital CMOS process. The filter nominally operates with a clock frequency of 10 MHz, cutoff frequency of 1 MHz, and a power supply of 2.3 V, while consuming 29 mW of power and processing input signals as large as 600-/spl mu/A peak differential. The low-charge injection nature of the circuit is reflected in its low total harmonic distortion of -59 dB for a 0.3-MHz signal with a modulation index of 0.5.

机译：本文提出了具有低电荷注入误差的数字CMOS开关电流（SI）电路。这些电路基于虚拟接地节点上的开关操作，以产生与信号无关的电荷注入。基于该方案，讨论了存储单元的不同拓扑。为了验证所开发的理论概念，在0.25- / spl mu / m数字CMOS工艺中实现了三阶椭圆低通SI滤波器。该滤波器通常以10 MHz的时钟频率，1 MHz的截止频率和2.3 V的电源工作，同时消耗29 mW的功率并处理高达600- / spl mu / A的峰值差分输入信号。该电路的低电荷注入特性体现在它对0.3 MHz信号，调制指数为0.5的低总谐波失真-59 dB的反映。

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来源
《IEEE Journal of Solid-State Circuits》 |2002年第10期|p.1271-1281|共11页
作者
Balachandran G.K.; Allen P.E.;
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作者单位

Analog Devices, Raleigh, NC, USA;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类无线电电子学、电信技术;
关键词
switched current circuits; switched filters; charge injection; CMOS integrated circuits; mixed analogue-digital integrated circuits; harmonic distortion; errors; elliptic filters; low-pass filters; circuit feedback; digital CMOS SI circuits; CMOS swi;

机译：开关电流电路;开关滤波器;电荷注入CMOS集成电路;混合模数集成电路;谐波失真错误;椭圆滤波器低通滤波器电路反馈;数字CMOS SI电路;CMOS扫描;

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专利

1. Switched-current circuits in digital CMOS technology with low charge-injection errors [J] . Balachandran G.K., Allen P.E. IEEE Journal of Solid-State Circuits . 2002,第10期

机译：具有低电荷注入误差的数字CMOS技术中的开关电流电路
2. An Efficient Design of Sequential Digital Circuits to Reduce Soft Errors in Nanoscale CMOS Technology [J] . K. Aditya, M. Sivakumar, B. K. V. Prasad, International Journal of Engineering Studies . 2012,第1期

机译：一种有效的顺序数字电路设计，可减少纳米级CMOS技术中的软错误
3. Fully differential switched-current memory cell with low charge-injection errors [J] . G.K.Balachandran, P.E.Allen IEE proceedings. Part G . 2001,第3期

机译：具有低电荷注入误差的全差分开关电流存储单元
4. Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow [C] . Abbas, M., Ikeda, . 2006

机译：可靠性驱动设计流程中CMOS数字电路中逻辑错误的统计模型
5. A switched-current filter in digital-CMOS technology with low charge-injection errors. [D] . Balachandran, Ganesh Kumar. 2001

机译：具有低电荷注入误差的数字CMOS技术中的开关电流滤波器。
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Switched-current circuits in digital CMOS technology with low charge-injection errors

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