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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A 43-Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology
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A 43-Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology

机译:基于InP的HEMT技术的43 Gb / s全速率时钟4:1多路复用器

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This paper describes a full-rate-clock 4:1 multiplexer (MUX) in a 0.13-Μm InP-based HEMT technology for 40-Gb/s and above optical fiber link systems. To reduce output jitter, the serialized data are retimed at the final stage by a retimer, a D-type flip-flop, which has a symmetric layout with an optimized spacing to the ground that minimizes coupling capacitances. A phase adjuster, composed of an exclusive OR and a delay switch, uses external control signals to change each phase of the serialized data and clock entering the retimer and gives a correct timing for the clock to drive the retimer. A clock distributor with a simple wired splitter divides the clock into two clocks with high gain and low current. The MUX integrates 1355 HEMTs formed using electron beam lithography. A chip mounted in a test module operated at up to 47 Gb/s with a power consumption of 7.9 W for a single supply voltage of -5.2 V.
机译:本文介绍了一种基于速率为0.13-μm基于InP的HEMT技术的全速率时钟4:1多路复用器(MUX),适用于40 Gb / s及以上的光纤链路系统。为了减少输出抖动,串行数据在最后阶段由重定时器D型触发器重新计时,该D型触发器具有对称布局,与地的最佳间距使耦合电容最小。由异或或延迟开关组成的相位调节器使用外部控制信号来改变串行数据的每个相位和进入重定时器的时钟,并为驱动重定时器的时钟提供正确的时序。具有简单有线分离器的时钟分配器将时钟分为高增益和低电流两个时钟。 MUX集成了1355个使用电子束光刻技术形成的HEMT。对于-5.2 V的单电源电压,安装在测试模块中的芯片以高达47 Gb / s的速度运行,功耗为7.9W。

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