An ultrahigh-density high-speed loadless four-transistor SRAM macrowith twisted bitline architecture and triple-well shield

Noda K.; Takeda K.; Matsui K.; Masuoka S.; Kawamoto H.; Ikezawa N.; Aimoto Y.; Nakamura N.; Iwasaki T.; Toyoshima H.; Horiuchi T.

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An ultrahigh-density high-speed loadless four-transistor SRAM macrowith twisted bitline architecture and triple-well shield

机译：具有扭曲位线架构和三阱屏蔽的超高密度高速无负载四晶体管SRAM宏

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We have developed two schemes for improving access speed andnreliability of a loadless four-transistor (LL4T) SRAM cell: andual-layered twisted bitline scheme, which reduces coupling capacitancenbetween adjacent bitlines in order to achieve highspeed READ/WRITEnoperations, and a triple-well shield, which protects the memory cellnfrom substrate noise and alpha particles. We incorporated these schemesnin a high-performance 0.18-Μm-generation CMOS technology andnfabricated a 16-Mb SRAM macro with a 2.18-Μm2 memory cell.nThe macro size of the LL4T-SRAM is 56 mm2, which is 30% ton40% smaller than a conventional six-transistor SRAM when compared withnthe same access speed. The developed macro functions at 500 MHz and hasnan access time of 2.0 ns. The standby current has been reduced to 25nΜA/Mb with a low-leakage nMOSFET in the memory cell

机译：我们开发了两种方案来提高无负载四晶体管（LL4T）SRAM单元的访问速度和可靠性：双层扭曲位线方案，该方案降低了相邻位线之间的耦合电容，从而实现了高速READ / WRITE操作，并采用了三阱屏蔽，可保护存储单元免受基板噪声和alpha颗粒的影响。我们将这些方案整合到了高性能的0.18μm代CMOS技术中，并制造了一个具有2.18μm2存储器单元的16Mb SRAM宏.n LL4T-SRAM的宏大小为56 mm2，比30％ton小40％。与相同的访问速度相比，传统的六晶体管SRAM。所开发的宏功能在500 MHz下运行，访问时间为2.0 ns。借助存储单元中的低泄漏nMOSFET，待机电流已降至25nΜA/ Mb

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来源
《IEEE Journal of Solid-State Circuits》 |2001年第3期|p.510-515|共6页
作者
Noda K.; Takeda K.; Matsui K.; Masuoka S.; Kawamoto H.; Ikezawa N.; Aimoto Y.; Nakamura N.; Iwasaki T.; Toyoshima H.; Horiuchi T.;
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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CMOS memory circuits; SRAM chips; alpha-particle effects; high-speed integrated circuits; integrated circuit noise; integrated circuit reliability; leakage currents; memory architecture; 0.18 micron; 16 Mbit; 2.0 ns; 500 MHz; CMOS; access speed; alpha particles; coupli;

机译：CMOS存储电路;SRAM芯片;阿尔法粒子效应;高速集成电路;集成电路噪声;集成电路可靠性;漏电流;存储器架构;0.18微米;16 Mbit;2.0 ns;500 MHz;CMOS;访问速度;alpha颗粒;coupli;

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专利

1. Quasi-worst-condition built-in-self-test scheme for a 4-Mb loadless CMOS four-transistor SRAM macro [J] . Koichi Takeda, Yoshiharu Aimoto, Kazuyuki Nakamura, 電子情報通信学会技術研究報告. 電子部品·材料. Component Parts and Materials . 2001,第517期

机译：4 Mb无负载CMOS四晶体管SRAM宏的准最坏条件内置自检方案
2. Quasi-worst-condition built-in-self-test scheme for a 4-Mb loadless CMOS four-transistor SRAM macro [J] . Koichi Takeda, Yoshiharu Aimoto, Kazuyuki Nakamura, 電子情報通信学会技術研究報告. 集積回路. Integrated Circuits and Devices . 2001,第519期

机译：4 Mb无负载CMOS四晶体管SRAM宏的准最坏条件内置自检方案
3. Quasi-worst-condition built-in-self-test scheme for a 4-Mb loadless CMOS four-transistor SRAM macro [J] . Koichi Takeda, Yoshiharu Aimoto, Kazuyuki Nakamura, 電子情報通信学会技術研究報告. 電子部品·材料. Component Parts and Materials . 2001,第517期

机译：用于4 MB无负载CMOS四晶体管SRAM宏的准差状况内置自检方案
4. An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield [C] . Noda, K., Matsui, . 2000

机译：具有双层扭曲位线和三阱屏蔽的超高密度高速无负载四晶体管SRAM宏
5. A high-speed, low-power three-dimensional-SRAM architecture. [D] . Nho, Hyunwoo. 2008

机译：高速，低功耗的三维SRAM架构。
6. A Shared-Bitline SRAM Cell Architecture for 1-V Ultra Low-Power Word-Bit Configurable Macrocells [O] . Hiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka 2013

机译：用于1 V超低功耗字位可配置宏单元的共享位线sRam单元架构

An ultrahigh-density high-speed loadless four-transistor SRAM macrowith twisted bitline architecture and triple-well shield

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