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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A CMOS ADSL codec for central office applications
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A CMOS ADSL codec for central office applications

机译:用于中心局应用的CMOS ADSL编解码器

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摘要

A CMOS central office codec that supports Full Rate and G.Litenasymmetric digital subscriber line (ADSL) transmission is described. Thentransmit channel consists of application-dependent digital filters, an14-bit, 8.832-MSample/s current steering DAC, a 1.104-MHz analog filter,nand a programmable attenuator. Due to extensive on-chip digital signalnprocessing, the codec complies with the ADSL transmit power spectralndensity standards without external filtering. The receive channelncontains -17.5 to 33.5 dB of programmable gain staggered strategicallynacross three stages, a 138-kHz analog low-pass filter, a 14-bit,n2.208-MSample/s pipeline ADC, and a digital 138-kHz low-pass filter. Thenreceive channel has a wide input range that can accommodate large linenvoltages present at the line hybrid circuit. The IC occupies 55.2nmm2 and dissipates 450 mW from a 3.3-V supply
机译:描述了一种支持全速率和G.Litenasymmetric数字用户线(ADSL)传输的CMOS中心局编解码器。然后,发射通道包括与应用相关的数字滤波器,14位,8.832-MSample / s的电流控制DAC,1.104MHz的模拟滤波器和可编程衰减器。由于广泛的片上数字信号处理,编解码器符合ADSL发射功率频谱密度标准,而无需外部滤波。接收通道n包含-17.5至33.5 dB的可编程增益,在三个阶段上策略性地错开分布:一个138 kHz模拟低通滤波器,一个14位,n2.208 MSample / s流水线ADC和一个数字138 kHz低通过滤。然后,接收通道具有较宽的输入范围,可以适应线性混合电路中存在的较大线性电压。该IC占地55.2nmm2,并通过3.3V电源消耗450mW的功率

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