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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A mixed-signal approach to high-performance low-power linearfilters
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A mixed-signal approach to high-performance low-power linearfilters

机译:高性能低功耗线性滤波器的混合信号方法

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We present a new approach to the design of high-performancenlow-power linear filters. We use p-channel synapse transistors as analognmemory cells, and mixed-signal circuits for fast low-power arithmetic.nTo demonstrate the effectiveness of our approach, we have built a 16-tapn7-b 200-MHz mixed-signal finite-impulse response (FIR) filter thatnconsumes 3 mW at 3.3 V. The filter uses synapse pFETs to store thenanalog tap coefficients, electron tunneling and hot-electron injectionnto modify the coefficient values, digital registers for the delay line,nand multiplying digital-to-analog converters to multiply the digitalndelay-line values with the analog tap coefficients. The measured maximumnclock speed is 225 MHz; the measured tap-multiplier resolution is 7 b atn200 MHz. The total die area is 0.13 mm2. We can readily scalenour design to longer delay lines
机译:我们提出了一种设计高性能低功率线性滤波器的新方法。我们使用p通道突触晶体管作为模拟存储器单元,并使用混合信号电路进行快速低功耗算术运算.n为了证明我们方法的有效性,我们建立了16-tapn7-b 200-MHz混合信号有限脉冲响应(FIR)滤波器在3.3 V时的功耗为3 mW。该滤波器使用突触pFET存储模拟分接系数,电子隧穿和热电子注入以修改系数值,延迟线的数字寄存器,以及将数模转换器乘以将digitalndelay-line值与模拟抽头系数相乘。测得的最大时钟速度为225 MHz;在200 MHz时,测得的抽头倍增器分辨率为7 b。模具总面积为0.13 mm2。我们可以轻松地将设计扩展到更长的延迟线

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