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首页> 外文期刊>IEEE Journal of Solid-State Circuits >VLSI implementation of a 100-ΜW multirate FSK receiver
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VLSI implementation of a 100-ΜW multirate FSK receiver

机译：100兆瓦多速率FSK接收机的VLSI实现

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A very low-power frequency-shift keying (FSK) receiver has beenndesigned for dual-purpose operation: deep space applications and generalnpurpose baseband processing. The receiver is based on a novel, almostnall-digital architecture. It supports a wide range of data rates and isnvery robust against large and fast frequency offsets due to Dopplerneffects. The architecture utilizes subsampling and l-b data processingntogether with an FFT-based detection scheme to enable power consumptionndramatically lower than a conventional implementation., Ansystem/hardware co-design approach allows the use of a number ofncircuit-level power reduction techniques while still meetingnsystem-level constraints. In particular, we designed a combination ofnfully parallel and word-serial decimation stages to simultaneouslynoptimize power consumption and silicon area. We also designed a verynefficient FFT block that uses approximate arithmetic and pruning tongreatly reduce overall complexity. Additional modules, such as directndigital frequency synthesizer (DDFS) and magnitude computation, havenalso been optimized in view of the targeted system parameters:nsignal-to-noise ratio and bit-error rate. The entire architecture hasnbeen made maximally flexible and power efficient by utilizing localnclock gating and simple interstage, handshaking mechanism. The receivernhas been implemented in 0.25-Μm CMOS technology and takes up under 1nmm2. The power consumption is below 100 ΜW for data ratesnbelow 20 kb/s. Rates up to 2 Mb/s are supported
机译：一种低功耗的频移键控（FSK）接收器已经设计用于双重用途：深空应用和通用基带处理。该接收器基于一种新颖的几乎所有数字的架构。它支持广泛的数据速率，并且对由于多普勒效应引起的大而快速的频率偏移非常不可靠。该架构利用子采样和lb数据处理以及基于FFT的检测方案，使功耗大大低于传统实现。系统/硬件协同设计方法允许使用多种电路级功耗降低技术，同时仍满足系统级功耗约束。特别是，我们设计了完全并行和字串行抽取阶段的组合，以同时优化功耗和硅面积。我们还设计了一个非常高效的FFT块，该块使用了近似算术，并通过修剪来降低总体复杂度。鉴于目标系统参数：信噪比和误码率，还优化了其他模块，例如直接数字频率合成器（DDFS）和幅度计算。通过使用localnclock门控和简单的级间握手机制，整个架构尚未实现最大的灵活性和高能效。接收器已采用0.25-μmCMOS技术实现，占用空间不到1nmm2。对于低于20 kb / s的数据速率，功耗低于100 MW。支持速率高达2 Mb / s

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