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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A serial-link transceiver based on 8-GSamples/s A/D and D/Aconverters in 0.25-Μm CMOS
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A serial-link transceiver based on 8-GSamples/s A/D and D/Aconverters in 0.25-Μm CMOS

机译:一个基于0.25-μmCMOS的8-GSamples / s A / D和D / A转换器的串行链路收发器

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摘要

This paper presents a transceiver that uses a 4-bit flashnanalog-to-digital converter (ADC) for the receiver and an 8-bitncurrent-steering digital-to-analog converter (DAC) for the transmitter.nThe 8-GSamples/s converters are 8-way time interleaved. Digitalncompensation reduces the input offset of the ADC comparators to lessnthan 0.6 LSB, improves the accuracy of the interleaved sampling clocksnto within 10 ps, and reduces systematic coupling noise to less than 18nmV on the 800-mV signal swing. 1.1-nH bondwire inductors distribute thenparasitic capacitances at the transceiver input and output, reducingnattenuation by 10 dB at 4 GHz. Equalization algorithms using thenconverters compensate for the 1.5-GHz transceiver bandwidth to allown8-GSamples/s multilevel data transmission
机译:本文介绍了一种收发器,该收发器使用4位闪存模拟到数字转换器(ADC)作为接收器,并使用8位电流控制数模转换器(DAC)作为发送器.n 8 GSamples / s转换器是8路时间交错。数字补偿可将ADC比较器的输入失调减小到小于0.6 LSB,将交错采样时钟的精度提高到10 ps以内,并在800 mV信号摆幅上将系统耦合噪声降低至18nmV以下。 1.1nH键合线电感在收发器的输入和输出端分布寄生电容,从而在4 GHz时将衰减降低10 dB。使用转换器的均衡算法可补偿1.5 GHz收发器带宽,从而实现8 GSamples / s的多级数据传输

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