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首页> 外文期刊>IEEE Journal of Solid-State Circuits >Noise and power reduction in filters through the use of adjustablebiasing
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Noise and power reduction in filters through the use of adjustablebiasing

机译:通过使用可调偏置来降低滤波器的噪声和功耗

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摘要

A technique that enables the variation of bias currents in anfilter without causing disturbances at the output is presented. Thus,nthe bias current can be kept at the minimum value necessary for thentotal input signal being processed, reducing the noise and powernconsumption. To demonstrate this approach, a dynamically biasednlog-domain filter has been designed in a 0.25-Μm BiCMOS technology.nThe chip occupies 0.52 mm2. In its quiescent condition, thenfilter consumes 575 ΜW and has an output noise of 4.4 nA rms.nSignal-to-noise ratio greater than 50 dB over 3 decades of input andntotal harmonic distortion less than 1% for inputs less than 2.5 mA peaknare achieved. The bias can be varied to minimize noise and powernconsumption without disturbing the output
机译:提出了一种能够在不引起输出干扰的情况下改变滤波器中偏置电流的技术。因此,可以将偏置电流保持在处理总输入信号所需的最小值,从而降低了噪声和功耗。为了证明这种方法,已经在0.25-μmBiCMOS技术中设计了一个动态偏置的对数域滤波器。该芯片占地0.52 mm2。在其静止状态下,滤波器会消耗575兆瓦的功率,输出噪声为4.4 nArms。n在连续输入30年的情况下,信噪比大于50 dB,对于总峰值小于2.5 mA的输入,总谐波失真小于1%。可以改变偏置以最大程度地降低噪声和功耗,而不会干扰输出

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