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首页> 外文期刊>IEEE Journal of Solid-State Circuits >A low-power reconfigurable analog-to-digital converter
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A low-power reconfigurable analog-to-digital converter

机译：低功耗可重构模数转换器

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A low-power CMOS reconfigurable analog-to-digital converter thatncan digitize signals over a wide range of bandwidth and resolution withnadaptive power consumption is described. The converter achieves the widenoperating range by (1) reconfiguring its architecture between pipelinenand delta-sigma modes; (2) varying its circuit parameters, such as sizenof capacitors, length of pipeline, and oversampling ratio, among others;nand (3) varying the bias currents of the opamps in proportion to thenconverter sampling frequency, accomplished through the use of anphase-locked loop (PLL). This converter also incorporates severalnpower-reducing features such as thermal noise limited design, globalnconverter chopping in the pipeline mode, opamp scaling, opamp sharingnbetween consecutive stages in the pipeline mode, an opamp choppingntechnique in the delta-sigma mode, and other design techniques. Thenopamp chopping technique achieves faster closed-loop settling time andnlower thermal noise than conventional design. At a converter powernsupply of 3.3 V, the converter achieves a bandwidth range of 0-10 MHznover a resolution range of 6-16 bits, and parameter reconfiguration timenof twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40nMHz. In the delta-sigma mode, it achieves a maximum signal-to-noisenratio of 94 dB and second and third harmonic distortions of 102 and 95ndB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6nmW power. In the pipeline mode, it achieves a maximum DNL and INL ofn±0.55 LSBs and ±0.82 LSBs, respectively, at 11 bits, at anclock frequency of 2.6 MHz and 1 MHz tone with 24.6 mW of power
机译：描述了一种低功率CMOS可重配置模数转换器，该转换器可以在很宽的带宽和分辨率范围内对信号进行数字化，且功耗不大。该转换器通过（1）在流水线模式和delta-sigma模式之间重新配置其架构来实现更大的工作范围； （2）改变其电路参数，例如电容器的尺寸，流水线的长度和过采样率等; nand（3）通过使用锁相来实现运算放大器的偏置电流与转换器采样频率成比例的变化环路（PLL）。该转换器还集成了数种降低功耗的功能，例如热噪声限制设计，流水线模式下的全局n转换器斩波，运算放大器缩放，流水线模式下连续级之间的运算放大器共享，delta-sigma模式下的运算放大器斩波技术以及其他设计技术。与传统设计相比，然后opopamp斩波技术可实现更快的闭环建立时间和更低的热噪声。在转换器电源为3.3 V的情况下，转换器在6-16位的分辨率范围内实现了0-10 MHz的带宽范围，并且具有十二个时钟周期的参数重新配置时间n。其PLL锁定范围在20 kHz至40nMHz范围内测量。在delta-sigma模式下，在10 MHz时钟频率，9.4 kHz带宽和17.6nmW功率下，其最大信噪比为94 dB，二次谐波和三次谐波失真分别为102和95ndB。在流水线模式下，它在11位，时钟频率为2.6 MHz和1 MHz且功率为24.6 mW的情况下，在11位时分别达到n±0.55 LSB和±0.82 LSB的最大DNL和INL。

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