CMOS stress sensors on (100) silicon

Jaeger R.C.; Suhling J.C.; Ramani R.; Bradley A.T.; Jianping Xu

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CMOS stress sensors on (100) silicon

机译：（100）硅上的CMOS应力传感器

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CMOS analog stress sensor circuits based upon the piezoresistivenbehavior of MOSFET's are presented. On the (100) surface, these circuitsnprovide temperature-compensated outputs that are proportional to thenin-plane normal stress difference (Σ(11)'-Σ22')nand the in-plane shear stress Σ22'. The circuitsnprovide high sensitivity to stress, well-localized stress-statenmeasurement, and direct voltage or current outputs that eliminate thenneed for tedious ΔR/R measurements required with more traditionalnresistor rosettes. The theoretical and experimental results also providendesign guidance for calculating and minimizing the sensitivity ofntraditional analog circuits to packaging-induced die stress

机译：提出了基于MOSFET的压阻行为的CMOS模拟应力传感器电路。在（100）表面上，这些电路提供了温度补偿输出，这些输出与面内法向应力差（Σ（11）'-Σ22'）n和面内切应力Σ22'成比例。该电路对应力具有很高的灵敏度，可以很好地进行局部应力状态测量，并且可以直接输出电压或电流，从而消除了传统电阻玫瑰花结所需的繁琐的ΔR/ R测量。理论和实验结果也为计算和最小化传统模拟电路对封装引起的芯片应力的敏感性提供了设计指导。

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来源
《IEEE Journal of Solid-State Circuits》 |2000年第1期|p.85-95|共11页
作者
Jaeger R.C.; Suhling J.C.; Ramani R.; Bradley A.T.; Jianping Xu;
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作者单位

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
中图分类一般性问题;基本电子电路;
关键词
CMOS analogue integrated circuits; microsensors; piezoresistive devices; stress measurement; (100) silicon substrate; CMOS stress sensor; MOSFET; Si; analog circuit; piezoresistive device; temperature compensation;

机译：CMOS模拟集成电路;微传感器;压阻器件;应力测量;（100）硅基板;CMOS应力传感器;MOSFET;Si;模拟电路;压阻器件;温度补偿;

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专利

1. CMOS stress sensors on [100] silicon [J] . Jaeger R.C., Suhling J.C. IEEE Journal of Solid-State Circuits . 2000,第1期

机译：[100]硅上的CMOS应力传感器
2. Investigations of Thermomechanical Stress Induced by TSV-Middle (Through-Silicon via) in 3-D ICs by Means of CMOS Sensors and Finite-Element Method [J] . Ewuame Komi Atchou, Fiori Vincent, Inal Karim, Components, Packaging and Manufacturing Technology, IEEE Transactions on . 2015,第8期

机译：通过CMOS传感器和有限元方法研究3-D IC中TSV中间层（硅通孔）引起的热机械应力
3. 3D TCAD simulations of strained Si CMOS devices with silicon-based alloy stressors and stressed CESL [J] . Wei-Ching Wang, Shu-Tong Chang, Jacky Huang, Solid-State Electronics . 2009,第8期

机译：带有硅基合金应力源和应力CESL的应变Si CMOS器件的3D TCAD模拟
4. CMOS stress sensor for 3D integrated circuits: Thermo-mechanical effects of Through Silicon Via (TSV) on surrounding silicon [C] . Ewuame Komi Atchou, Fiori Vincent, Inal Karim, International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems . 2014

机译：用于3D集成电路的CMOS应力传感器：硅通孔（TSV）对周围硅的热机械效应
5. Design, fabrication, and characterization of tungsten/silicon germanium/silicon raised single source/drains for sub-100nm CMOS and sub-70nm fully self-aligned double-gated CMOS [D] . Gan, Dong 2000

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6. Proximity Gettering Design of Hydrocarbon–Molecular–Ion–Implanted Silicon Wafers Using Dark Current Spectroscopy for CMOS Image Sensors [O] . Kazunari Kurita, Takeshi Kadono, Satoshi Shigematsu, 2019

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CMOS stress sensors on (100) silicon

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